Abstract: A image sensor has a plurality of microlens disposed across an image area in which centrally disposed red pixels are provided with smaller microlenses and peripherally disposed red pixels are provided with larger microlenses. The size differential, which amounts to a small percentage to compensate for a refractivity differential per wavelength of incident light across the image area, prevents the generation of a reddish effect in an output image. The image sensor includes a color filter array having separate color filters including a long-wavelength filter, and a plurality of microlenses respectively formed on the separate color filters, wherein the microlenses corresponding to the long-wavelength filter have relative sizes differing according to disposition with respect to the color filter array.

Abstract: A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant region, forms spacers on sidewalls of the pad nitride layer pattern, removes some part of the pad oxide layer and the top portion of the substrate through an etching process using the spacers as a mask to form a trench that divides the ion implant region into two parts. The example fabrication method also forms a gap filling insulating layer over the resulting substrate, and forms a trench isolation layer and junction regions simultaneously by removing the spacers, the pad nitride layer pattern, the pad oxide layer, and the top portion of the gap filling insulating layer.

Abstract: Methods for forming a gate in a semiconductor device are disclosed. In an example method, the gate is formed such that the CD of an upper portion of the gate is greater than the CD of a lower portion of the gate by performing multiple etching processes. In an illustrated example, the etching processes are performed in three stages, (i.e., a first dry etching process for etching the upper portion, a second dry etching process for etching the lower portion and a third dry etching) under three different process conditions, thereby causing a sidewall profile of the gate to have a two-layered structure.