Abstract: An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive type base area on the second conductive type buffer layer; a gate on the substrate at a side of the first conductive type base area; a second conductive type emitter ion implantation area in the first conductive type base area; an insulating layer on the gate; an emitter electrode electrically connected to the second conductive type emitter ion implantation area; and a collector electrode electrically connected to the first conductive collector ion implantation area.

Abstract: A method of manufacturing a CMOS image sensor comprising forming a first insulating film on a silicon semiconductor substrate which includes a metal pad; selectively etching the first insulating film, so as to form a first insulating film pattern with a first opening which exposes the metal pad; forming a metal pad protective film in the first opening portion with a predetermined thickness; forming a second insulating film on the first insulating film pattern and metal pad protective film; selectively etching the second insulating film, so as to form a second insulating film pattern which includes a second opening which exposes the metal pad protective film; forming a color filter array (CFA) on the second insulating film pattern; forming micro lenses on the CFA; and performing an etching process in order to remove the metal pad protective film so as to form a metal pad opening.

Abstract: An equivalent circuit of an inductor is provided with a five wire structure. A first wire has a first resistor, an inductor, and a third resistor connected in series. A second wire is connected in parallel with the first wire and has a second resistor. A third wire is connected in parallel with the first and second wires and has a third capacitor. A fourth wire is serially connected to a first common node of the first, second, and third wires, and has a first capacitor connected between the first common node and a first sub capacitor and a first sub resistor connected in parallel. A fifth wire is serially connected to a second common node of the first, second, and third wires, and has a second capacitor connected between the second common node and a second sub capacitor and a second sub resistor connected in parallel.