Abstract: The method for full-chip quick simulation of negative tone development photolithography process, analyze the elastic deformation of the photoresist based on elastic mechanics, sets one of the stress and strain variables as an equivalent of a deformation of the photoresist, to obtain an equivalent equation, performs an approximate calculation of the equivalent equation using a Taylor expansion formula to obtain an approximate value of stress or strain, and adjusts the light field distribution according to the approximate value to obtain an appropriate acid concentration distribution, which can make the exposed image closest to a target image. It can effectively analyze the deformation of the photoresist during the thermal shrinkage effect process and improve the accuracy of the lithography calculation process. At the same time, the Taylor expansion is used to fit the thermal shrinkage effect, which can improve the calculation speed.

Abstract: The method for simulation of negative tone development photolithography process, includes following steps: S1, divide a selected photoresist region into finite elements to obtain a plurality of lattice units based on a finite element analysis method; S2, set deformation of photoresist as elastic deformation, equivalent an irradiation effect of a light field on the lattice units to a force, perform stress analysis on a lattice unit based on elastic mechanics, generate a unit stiffness matrix of each lattice unit based on a relationship between stress and strain, and form an overall stiffness matrix of the photoresist region based on generated unit stiffness matrix of each lattice unit; S3, define the stresses on nodes of each lattice unit as node forces, obtain equivalent node forces of each lattice unit, and obtain overall node forces matrix of the photoresist region based on obtained equivalent node forces; S4, solve the overall stiffness matrix and the overall node force matrix, and calculate an overall dis

Abstract: Methods and apparatuses are provided for data processing. The method includes receiving a first data packet and a second data packet; associating first codes with the first data packet and second codes with the second data packet to generate a combined data packet after receiving the first data packet and the second data packet, wherein the first codes and the second codes specify processing to be performed to the a combined data packet; generating the combined data packet comprising the first data packet and the second data packet in response to determining that the first data packet and the second data packet are correlated; and performing the processing to the combined data packet in accordance with the first codes or the second codes.

Abstract: Methods and apparatuses are provided for data processing. The method includes receiving a data packet; associating codes with the data packet, wherein the codes specify processing to be performed to the data packet; and performing the processing to the data packet in accordance with the codes. The apparatus includes a receiver, configured to receive a data packet; a processor; and a memory coupled to the processor, the memory configured to store instructions which when executed by the processor become operational with the processor to: associate codes with the data packet, wherein the codes specify processing to be performed to the data packet; and perform the processing to the data packet in accordance with the codes.

Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.

Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes generating care areas that each includes at least one potential defect, organizing the generated care areas based on a first set of spatial relationships to provide a list of neighboring care areas, wherein each neighboring care area is an entry within the list, and generating a recipe file of the list, wherein each neighboring care area is inspected sequentially using a high-resolution inspection system. The system comprises a memory including instructions executable by a processor to: generate care areas that each includes at least one potential defect, organize the generated care areas based on a first set of spatial relationships to provide a list of neighboring care areas that are each an entry within the list, and generate a recipe file of the list, wherein each neighboring care area is inspected sequentially using a high-resolution inspection system.

Abstract: A method for imaging a surface of a substrate using a multi-beam imaging system includes: modifying an electron beam using a multipole-field device; generating beamlets from the electron beam using a beam-splitting device having multiple apertures; in response to projecting foci of the beamlets onto the surface, driving the beamlets using a deflector set to scan a region of the surface for receiving signals based on electrons scattered from the region; and determining an image of the region for inspection based on the signals. The multi-beam imaging system includes: an electron source; a first multipole-field device for beam shaping and beam aberration correction; a beam-splitting device; a projection lens set; a deflector set; an objective lens set; a detector array; a second multipole-field device; a processor; and a memory storing instructions to determine an image of the region for inspection based on the signals.

Abstract: Methods, apparatuses and systems for classifying defects for a defect inspection system are disclosed. The defect inspection system can be used to inspect and manage wafer or reticle defects. The method includes receiving a defect record based on an inspection of a target specimen, the defect record comprising a defect image associated with an unknown defect, selecting, by a computing device using a first processing unit, components ranked by significance from the defect image using a first learning technique, and determining, by the computing device using the first processing unit, whether the defect image is associated with a known defect type based on the components ranked by significance using a second learning technique.

Abstract: Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.

Abstract: A method for reference image contour generation includes generating a mask pattern based on design target information, generating a reference image based on a simulation of photolithographic effects on the mask pattern, generating a reference image contour pattern based on edge detection in the reference image, and generating a scanned image contour pattern as a function of the reference image contour pattern and a scanned image of an integrated circuit.

Abstract: A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.

Abstract: Techniques for yield management in semiconductor inspection systems are described. According to one aspect of the present invention, an electron beam inspection system includes multiple stages or multiple chambers, where the chambers/stages (N?2) are organized to form one or more paths for wafer/mask inspection. An inspection procedure in each chamber (or at each stage) is determined by its order in the path and the relative columns used. For a system with N chambers/stages, a maximum number of N wafers/masks can be processed simultaneously.

Abstract: A method for managing defects for an augmented automatic defect classification (ADC) process is disclosed. The method includes receiving a defect record based on an inspection of a target specimen; extracting, from a design database, relevant design data associated with a patch surrounding a location of a defect from the defect record; performing, by a processor, lithographic simulation on the relevant design data associated with the patch to determine a context patch; comparing, by the processor, the context patch with an image of the defect from the defect record to determine whether there exists a match between the context patch and the image of the defect; and defining the defect as a systematic defect based on a determination that there exists a match between the context patch and the image of the defect.

Abstract: A drive mechanism to move an optical component sensitive to particles is described. The drive mechanism has high precision in rotation, great reliability and durability life, no backlash, and far less particle contamination. The drive mechanism can be advantageously used in high precision rotation driving processes for opto-mechanical inspection systems that require high movement precision and no-contamination. In one embodiment, two pulleys are used with their axes to be parallel from each other, two bands are used to rotate the pulleys in opposite directions. An eccentric disk mechanism is used to fine-tune the distance between the two pulleys so that tensions on the two bands can be optimized.