Abstract: A method, a non-transitory computer-readable medium, and an apparatus for optimizing a design layout of an integrated circuit (IC) includes: selecting layout regions from a full-chip design layout for the IC; determining pixel images for the layout regions by performing pixel-based mask optimization for the layout regions, in which each pixel image corresponds to a respective layout region; determining a backpropagation (BP) artificial neural network (ANN) model using the pixel images and the layout regions; and determining a full-chip pixel image for the full-chip design layout using the BP ANN model, in which the BP ANN model uses the full-chip design layout as input.
Type:
Grant
Filed:
May 9, 2017
Date of Patent:
December 31, 2019
Assignees:
Shenzhen Jingyuan Information Technology Limited, Dongfang Jinigryuan Electron Limited
Inventors:
Zongchang Yu, Shengrui Zhang, Weijie Shi