Abstract: An OFDM receiver includes a sampling circuit configured to sample an incoming signal received through a transmission channel and an estimation circuit configured to receive samples of the incoming signal and to estimate transmission channel response and eventual differences of synchronization offsets introduced at a receiver side. An equalizer may be coupled to the estimation circuit and configured to compensate an effect of the transmission channel response and of the differences of synchronization offsets on the received samples and to generate equalized samples. An OFDM detector may be configured to generate a stream of demodulated digital symbols based upon the equalized samples.

Abstract: There is described a detecting device of the distribution profile of current of a switching converter; the converter has an input voltage and is adapted to supply an output current. The device comprises means adapted to convert a signal indicating the output current of the converter into a digital signal comprising p digital samples, being p an integer, processed in p successive time intervals belonging to a time period.

Abstract: The recognition of a frame synchronization pattern or unique word of a received signal may be enhanced using a data-aided estimator of the signal-to-noise ratio (SNR) together with a correlation detector of the unique word to be received. Detecting a frame synchronization pattern or a unique word in a received signal, the SNR is estimated on the received signal with a data-aided SNR estimator using the unique word to be received. If the estimated SNR exceeds a certain threshold, an eventual recognition of the unique word established by a correlation correlator of the receiver is considered reliable. Comparing the SNR with the threshold may be carried out either before or after the correlator has processed the unique word.

Abstract: The method transmits a long packet of digital data over a poly-phase power line affected by impulsive noise synchronous with phase voltages. Instead of using very complicated coding schemes, starting from the knowledge of the typical power line scenario, useful information is transmitted where noise synchronous with the main signal is absent. Time-intervals of a known or estimated duration during which the poly-phase power line is affected by impulsive noise are determined, and dummy data during the time-intervals, and useful data during other time-intervals free from impulsive noise, are transmitted.

Abstract: A method of driving a stepper motor in a feed-forward voltage mode may include for a desired speed for the stepper motor setting an amplitude of a sinusoidal phase voltage of the stepper motor to be equal to a sum of an expected back-electromotive force (BEMF) amplitude estimated as a junction of the desired speed, and a product of a desired phase current amplitude and an estimated absolute value of an impedance of the stepper motor.

Abstract: A method of estimating a signal-to-noise ratio from a received M-DPSK modulated signal, comprising a sequence of N known symbols, based on a division of the known symbols N and of N samples of the received signal at the output of the channel into a number of blocks B of length L with B greater than one.

Abstract: A control device for a switching converter, the converter having at least one transistor supplied by an input voltage and adapted to supply a load by means of an output voltage. The converter also including a circuit adapted to turn on and off the at least one transistor. The control device includes an operation circuit adapted to change the state of the at least one transistor from turned on to turned off or vice versa, respectively when the output voltage goes down or goes up by a first voltage of a given value by defining a first state; the operation circuit including a further circuit adapted to generate a ramp signal and to change the first state of the at least one transistor from turned on to turned off or vice versa when the ramp voltage is equal to the output voltage of the converter.

Abstract: A control system for a switching DC-DC converter is proposed. The converter includes an input terminal for receiving an input voltage from a source, a control terminal adapted to receive a switching control signal, and an output terminal for providing to a load an output voltage generated from the input voltage according to the control signal. The control system includes detecting means for detecting a reaching condition of a predetermined value by a current provided to the load by the converter and control means for controlling the control signal according to the output voltage. The control system further includes disabling means for disabling the supply of the control signal to the control terminal according to the detection of the reaching condition. The disabling means includes selection means for controlling the disabling according to a time relationship between the detection of the reaching condition and the control signal.

Abstract: A voltage multiplier includes a control circuit that generates first and second signals in phase opposition and a charging section. The latter comprises a first capacitor having a first terminal coupled to the first signal and a second capacitor having a first terminal coupled with the second signal. The multiplier includes respective parasitic capacitances placed respectively between the capacitors and a reference voltage. The charging section is coupled with an input voltage and is suitable for producing an output voltage that is a multiple of the constant voltage. The multiplier comprises a switch that selectively connects the parasitic capacitances to carry out a charge transfer from one parasitic capacitance to the other.

Abstract: A method for loading bits over a set of subcarriers of a multiple-carrier communications system comprises the operation of associating with the subcarriers respective numbers of bits chosen from among a plurality of available constellations. The method envisages definition of a performance target for the system and execution of bit loading, guaranteeing the aforesaid target on a plurality of subcarriers. The performance target can be a target error rate, such as a bit-error rate (BER), or else be transferred into a constraint, such as, for example, a threshold, in a metric of log-likelihood ratios (LLRs). In this case, there is preferably envisaged application to the signals received within the multiple-carrier system a function that estimates a signal to noise ratio on each sub-carrier. The aforesaid metric of log-likelihood ratios (LLRs) is hence defined as a function of said signal to noise ratios.

Abstract: An electronic synchronous/asynchronous transceiver device for power line communication networks is integrated into a single chip and operates from a single supply voltage. The transceiver device includes: at least an internal register that is programmable through a synchronous serial interface; at least a line driver for a two-way network communication over power lines implemented by a single ended power amplifier with direct accessible input and output lines that is part of a tunable active filter for the transmission path; and at least a couple of linear regulators for powering with different voltage levels different kind of external controllers linked to the transceiver device.

Abstract: An electric circuit includes a circuit path from a first reference voltage to a second reference voltage lower than the first reference voltage. The path includes a current generator, a capacitor, a first switching element suitable for connecting or disconnecting the capacitor with respect to the current generator. The first switching element has a triggering value and the electric circuit includes a second switching element placed in parallel to the capacitor and control elements suitable for acting on the first and second switching elements for controlling the charging and discharging of the capacitor. The control elements comprise a comparator operable during the charging of the capacitor and suitable for acting on the first switching element for blocking the charging of the capacitor when the voltage value at its terminals reaches a threshold voltage value. The threshold voltage value is lower than the triggering voltage of the first switching element and higher than the second reference voltage.

Abstract: Log-likelihood ratios are approximated for encoded bits modulated with a 2m-ary QAM constellation. Each symbol of the constellation is identified by a respective string of m bits. The log-likelihood ratio of each bit of the m bits is approximated with a product ? of a respective factor by a respective variable D that depends on a received signal and on communication channel characteristics. The approximating includes determining a value of at least one of the variables D using a parametric nonlinear function of an equalized replica ? of a respective received signal.

Abstract: A voltage multiplier includes a control circuit that generates first and second signals in phase opposition and a charging section. The latter comprises a first capacitor having a first terminal coupled to the first signal and a second capacitor having a first terminal coupled with the second signal. The multiplier includes respective parasitic capacitances placed respectively between the capacitors and a reference voltage. The charging section is coupled with an input voltage and is suitable for producing an output voltage that is a multiple of the constant voltage. The multiplier comprises a switch that selectively connects the parasitic capacitances to carry out a charge transfer from one parasitic capacitance to the other.

Abstract: An electric circuit includes a circuit path from a first reference voltage to a second reference voltage lower than the first reference voltage. The patha current generator, a capacitor, a first switching element suitable for connecting or disconnecting the capacitor with respect to the current generator. The first switching element has a triggering value and the electric circuit includes a second switching element placed in parallel to the capacitor and control elements suitable for acting on the first and second switching elements for controlling the charging and discharging of the capacitor. The control elements comprise a comparator operable during the charging of the capacitor and suitable for acting on the first switching element for blocking the charging of the capacitor when the voltage value at its terminals reaches a threshold voltage value. The threshold voltage value is lower than the triggering voltage of the first switching element and higher than the second reference voltage.

Abstract: A method creates a display device driverby steps including: considering transmittance characteristics in relation to voltages applied to plural liquid crystal displays; defining a transmittance curve based on the voltage applied to said displays, for each display; applying a gamma correction, with different values of the gamma exponent, to each transmittance curve; applying a kickback correction to each curve; positioning branch points along said curves; determining a resistance value for each branch point and for each curve for each display; choosing a minimum resistance value for each branch point; choosing a maximum resistance value of for each branch point; calculating the difference between said minimum resistance value and said maximum resistance value for each branch point; defining for each branch point a fixed resistance value equal to said minimum resistance value; defining for each branch point an interval of values for a variable resistance equal to said difference.

Abstract: A method for driving low consumption LCD modules, the LCD modules having a multiplicity of display elements located at the intersections of a matrix having a plurality of row electrodes and a plurality of column electrodes, the method includes the phases of applying an M bit electrical digital signal to at least one row electrode at a time, subdivided in a plurality of time intervals equal to 2M?1, the electrical digital signal suitable for illuminating each of the display elements with a predefined luminosity level chosen from among 2M luminosity levels, each of the M bits is applied for a preset duration, then reducing the preset duration of each of the M bits in accordance with a predefined scale factor K and subdividing the M bits in (2M?1)/K plurality of time intervals.

Abstract: The present invention relates to a driving method for flat panel display devices, particularly a driving method combining a Multi Line Addressing (MLA) technique and a Frame Rate Control (FRC) technique, for flat panel display devices such as Liquid Crystal Display (LCD).