Patents Assigned to Dorado Design Automation, Inc.
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Patent number: 7992123Abstract: A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis with optimization of the first and second HDL codes while forcibly preserving elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second and third circuit to generate at least one ECO cone-pair; and obtaining an ECO logic and an element to be replaced according to the ECO cone-pair and the post layout circuit, and then replacing the element to be replaced in the post layout circuit with the ECO logic gate circuit, thereby modifying the post layout circuit into a post layout ECO circuit.Type: GrantFiled: March 10, 2008Date of Patent: August 2, 2011Assignee: Dorado Design Automation, Inc.Inventor: Chien-Jung Hsin
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Patent number: 7555737Abstract: For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is processed to obtain a first timing data. The first timing data is then inputted for timing verification of the first netlist. If the first netlist does not pass the verification, the first netlist is modified into a second netlist, while defining a modified portion of the netlist. Then, the modified portion of netlist is processed to obtain a second timing data, and the second timing data is used to overwrite a part of the first timing data. The first physical design is modified into a second physical design according to the second netlist only when the second netlist with the first timing data overwritten by the second timing data passes the timing verification, thereby improving time efficiency.Type: GrantFiled: November 29, 2006Date of Patent: June 30, 2009Assignee: Dorado Design Automation, Inc.Inventors: Hsien Ming Liu, Chien Jung Hsin, Jun Jyeh Hsiao, Sheng Chun Lee, Chun Wei Lo
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Publication number: 20080222595Abstract: A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis with optimization of the first and second HDL codes while forcibly preserving elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second and third circuit to generate at least one ECO cone-pair; and obtaining an ECO logic and an element to be replaced according to the ECO cone-pair and the post layout circuit, and then replacing the element to be replaced in the post layout circuit with the ECO logic gate circuit, thereby modifying the post layout circuit into a post layout ECO circuit.Type: ApplicationFiled: March 10, 2008Publication date: September 11, 2008Applicant: DORADO DESIGN AUTOMATION, INC.Inventor: Chien-Jung Hsin
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Publication number: 20070124712Abstract: For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is processed to obtain a first timing data. The first timing data is then inputted for timing verification of the first netlist. If the first netlist does not pass the verification, the first netlist is modified into a second netlist, while defining a modified portion of the netlist. Then, the modified portion of netlist is processed to obtain a second timing data, and the second timing data is used to overwrite a part of the first timing data. The first physical design is modified into a second physical design according to the second netlist only when the second netlist with the first timing data overwritten by the second timing data passes the timing verification, thereby improving time efficiency.Type: ApplicationFiled: November 29, 2006Publication date: May 31, 2007Applicant: DORADO DESIGN AUTOMATION, INC.Inventors: Hsien Ming Liu, Chien Jung Hsin, Jun Jyeh Hsiao, Sheng Chun Lee, Chun Wei Lo