Abstract: Disclosed herein is a multi-bank type semiconductor memory device which reduces current consumption of data lines. In the multi-bank type semiconductor memory device according to the present invention, the data lines between each memory bank and an input/output buffer are divided into horizontal data lines and vertical data lines. In addition, a high impedance driver is provided to drive horizontal local data of the horizontal data line to provide the horizontal local data as vertical local data of the vertical data line. Therefore, in the multi-bank type semiconductor memory device according to the present invention, even when the horizontal local data and the vertical local data are controlled at a low power voltage, degradation in overall operating speed hardly occurs. In addition, in the multi-bank type semiconductor memory device according to the present invention, current consumption in the data lines is significantly reduced.

Abstract: A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.

Abstract: A NAND flash memory device having a facing bar and a method of fabricating the same are provided. The method includes forming one transistor or a plurality of stack transistors as cell transistors on two side surfaces of a facing bar to have transmission channels thereat. In this case, the height of the facing bar may be easily increased. Thus, not only a layout area of unit transistors including the cell transistors but also a layout area of cell strings may be minimized, and lengths of the transmission channels of the cell transistors may be sufficiently extended. As a result, according to the NAND flash memory device and the method of fabricating the same, the overall operating characteristics are improved.

Abstract: A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.

Abstract: A NAND flash memory device having a facing bar and a method of fabricating the same are provided. The method includes forming one transistor or a plurality of stack transistors as cell transistors on two side surfaces of a facing bar to have transmission channels thereat. In this case, the height of the facing bar may be easily increased. Thus, not only a layout area of unit transistors including the cell transistors but also a layout area of cell strings may be minimized, and lengths of the transmission channels of the cell transistors may be sufficiently extended. As a result, according to the NAND flash memory device and the method of fabricating the same, the overall operating characteristics are improved.

Abstract: The fabricating method of a DRAM cell includes forming a facing bar that extends in a direction of the word line; forming a gate of the cell transistor on one side surface of the facing bar; forming a bit line plug that is electrically connected to one side of the transmission channel, which is formed on the one side surface of the facing bar; and forming the storage that is electrically connected to the other side of the transmission channel, which is formed on the horizontal surface of the semiconductor substrate. A pair of DRAM cells shares a facing bar and a bit line plug. In accordance with the present disclosure, a required layout area is significantly reduced.

Abstract: The fabricating method of a DRAM cell includes forming a facing bar that extends in a direction of the word line; forming a gate of the cell transistor on one side surface of the facing bar; forming a bit line plug that is electrically connected to one side of the transmission channel, which is formed on the one side surface of the facing bar; and forming the storage that is electrically connected to the other side of the transmission channel, which is formed on the horizontal surface of the semiconductor substrate. A pair of DRAM cells shares a facing bar and a bit line plug. In accordance with the present disclosure, a required layout area is significantly reduced.