Patents Assigned to Dover Microsystems, Inc.
  • Patent number: 12645798
    Abstract: Systems and methods for on-demand loading of metadata. In some embodiments, in response to receiving a page fault service request from an operating system kernel, at least one first physical page may be allocated in an application memory for a virtual address indicated in the page fault service request. Metadata may be loaded into at least one second physical page in a metadata memory, wherein: the at least one second physical page in the metadata memory corresponds to the at least one first physical page in the application memory; and the metadata loaded into the at least one second physical page corresponds to application data loaded into the at least one first physical page.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: June 2, 2026
    Assignee: Dover Microsystems, Inc.
    Inventors: Eli Boling, Steven Milburn
  • Patent number: 12530220
    Abstract: Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor.
    Type: Grant
    Filed: December 15, 2023
    Date of Patent: January 20, 2026
    Assignee: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Gregory T. Sullivan
  • Patent number: 12524394
    Abstract: Systems and methods for updating metadata. In some embodiments, in response to detecting an instruction executed by a hardware system, a source location of the instruction may be identified. First metadata associated with the instruction may be used to determine whether the instruction is allowed. In response to determining that the instruction is allowed, the source location of the instruction may be associated with second metadata.
    Type: Grant
    Filed: July 19, 2024
    Date of Patent: January 13, 2026
    Assignee: Dover Microsystems, Inc.
    Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland
  • Publication number: 20250390572
    Abstract: Systems and methods for metadata processing. In some embodiments, one or more metadata inputs may be processed to determine whether to allow an instruction. For instance, one or more classification bits may be identified from a metadata input of the one or more metadata inputs, and the metadata input may be processed based on the one or more classification bits.
    Type: Application
    Filed: June 3, 2025
    Publication date: December 25, 2025
    Applicant: DOVER MICROSYSTEMS, INC.
    Inventors: Andrew SUTHERLAND, Steven MILBURN, Gregory T. SULLIVAN, Eli BOLING
  • Publication number: 20250348599
    Abstract: Systems and methods for enforcing one or more policies that are encoded as programmable hardware functions. In some embodiments, tag processing hardware may receive information relating to one or more instructions executed by a host system. The information may be used to construct an input pattern, which may be processed, in hardware, to obtain at least one indicator. The tag processing hardware may then determine whether the at least one indicator matches at least one parameter that is selected based on one or more policies being enforced by the tag processing hardware. In response to determining that the at least one indicator does not match the at least one parameter, the tag processing hardware may send a signal to the host system to indicate a violation of the one or more policies.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 13, 2025
    Applicant: DOVER MICROSYSTEMS, INC.
    Inventors: Andrew SUTHERLAND, Steven MILBURN
  • Patent number: 12393677
    Abstract: Systems and methods for metadata processing. In some embodiments, one or more metadata inputs may be processed to determine whether to allow an instruction. For instance, one or more classification bits may be identified from a metadata input of the one or more metadata inputs, and the metadata input may be processed based on the one or more classification bits.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 19, 2025
    Assignee: Dover Microsystems, Inc.
    Inventors: Andrew Sutherland, Steven Milburn, Gregory T. Sullivan, Eli Boling
  • Patent number: 12373314
    Abstract: In some embodiments, a system is provided, comprising enforcement hardware configured to execute, at run time, a state machine in parallel with application code. Executing the state machine may include: maintaining metadata that corresponds to one or more state variables of the state machine; matching instructions in the application code to transitions in the state machine; and, in response to determining that an instruction in the application code does not match any transition from a current state of the state machine, causing an error handling routine to be executed. In some embodiments, a description of a state machine may be translated into at least one policy to be enforced at run time based on metadata labels associated with application code and/or data manipulated by the application code.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: July 29, 2025
    Assignee: Dover Microsystems, Inc.
    Inventors: Andrew Sutherland, Jonathan B. Rosenberg, Gregory T. Sullivan
  • Publication number: 20250208998
    Abstract: Systems and methods for caching metadata. In some embodiments, in response to an access request comprising an application memory address, it may be determined whether the application memory address matches an entry of at least one cache. In response to determining that the application memory address does not match any entry of the at least one cache: the application memory address may be used to retrieve application data; the application memory address may be mapped to at least one metadata memory address; and the at least one metadata memory address may be used to retrieve metadata corresponding to the application memory address. An entry in the at least one cache may be created, wherein: the entry is indexed by the application memory address; and the entry stores both the application data retrieved using the application memory address, and the corresponding metadata retrieved using the at least one metadata memory address.
    Type: Application
    Filed: March 14, 2025
    Publication date: June 26, 2025
    Applicant: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Nirmal Nepal
  • Publication number: 20250138824
    Abstract: Systems and methods for updating metadata. In some embodiments, processing hardware may receive an input metadata pattern associated with an instruction executed by a host processor. The input metadata pattern may comprise: one or more first input metadata labels associated with the instruction and/or a state of the host processor; and one or more second input metadata labels associated, respectively, with one or more registers used by the instruction and/or one or more memory locations referenced by the instruction. The processing hardware may generate an output metadata pattern, wherein: the one or more first input metadata labels are used to determine how to process the one or more second input metadata labels to generate the output metadata pattern.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Applicant: DOVER MICROSYSTEMS, INC.
    Inventor: Steven MILBURN
  • Patent number: 12253944
    Abstract: Systems and methods for caching metadata. In some embodiments, in response to an access request comprising an application memory address, it may be determined whether the application memory address matches an entry of at least one cache. In response to determining that the application memory address does not match any entry of the at least one cache: the application memory address may be used to retrieve application data; the application memory address may be mapped to at least one metadata memory address; and the at least one metadata memory address may be used to retrieve metadata corresponding to the application memory address. An entry in the at least one cache may be created, wherein: the entry is indexed by the application memory address; and the entry stores both the application data retrieved using the application memory address, and the corresponding metadata retrieved using the at least one metadata memory address.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: March 18, 2025
    Assignee: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Nirmal Nepal
  • Publication number: 20250086162
    Abstract: Systems and methods for updating metadata. In some embodiments, in response to detecting an instruction executed by a hardware system, a source location of the instruction may be identified. First metadata associated with the instruction may be used to determine whether the instruction is allowed. In response to determining that the instruction is allowed, the source location of the instruction may be associated with second metadata.
    Type: Application
    Filed: July 19, 2024
    Publication date: March 13, 2025
    Applicant: Dover Microsystems, Inc.
    Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland
  • Patent number: 12248564
    Abstract: According to at least one aspect, a hardware system include a host processor, a policy engine, and an interlock is provided. These components can interoperate to enforce security policies. The host processor can execute an instruction and provide instruction information to the policy engine and the result of the executed instruction to the interlock. The policy engine can determine whether the executed instruction is allowable according to one or more security policies using the instruction information. The interlock can buffer the result of the executed instruction until an indication is received from the policy engine that the instruction was allowable. The interlock can then release the result of the executed instruction. The policy engine can be configured to transform instructions received from the host processor or add inserted instructions to the policy evaluation pipeline to increase the flexibility of the policy engine and enable enforcement of the security policies.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: March 11, 2025
    Assignee: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Eli Boling
  • Patent number: 12242575
    Abstract: A system including at least one processor programmed to identify, based on a policy to be enforced, one or more metadata symbols corresponding to an entity name; identify, from a target description describing a target system, an entity description matching the entity name, wherein the entity description describes an entity of the target system; and apply a metadata label to the entity of the target system, wherein the metadata label is based on the one or more metadata symbols corresponding to the entity name, as identified based on the policy.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: March 4, 2025
    Assignee: Dover Microsystems, Inc.
    Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland
  • Publication number: 20240419783
    Abstract: Systems and methods for compartmentalization. In some embodiments, in response to receiving a compartment update request, a target compartment of a compartment transition triggering the compartment update request may be determined, and a compartment configuration corresponding to the target compartment may be loaded, wherein the compartment configuration indicates at least one address range associated with the target compartment.
    Type: Application
    Filed: June 18, 2024
    Publication date: December 19, 2024
    Applicant: Dover Microsystems, Inc.
    Inventor: Andrew Sutherland
  • Publication number: 20240394362
    Abstract: According to at least one aspect, a hardware system include a host processor, a policy engine, and an interlock is provided. These components can interoperate to enforce security policies. The host processor can execute an instruction and provide instruction information to the policy engine and the result of the executed instruction to the interlock. The policy engine can determine whether the executed instruction is allowable according to one or more security policies using the instruction information. The interlock can buffer the result of the executed instruction until an indication is received from the policy engine that the instruction was allowable. The interlock can then release the result of the executed instruction. The policy engine can be configured to transform instructions received from the host processor or add inserted instructions to the policy evaluation pipeline to increase the flexibility of the policy engine and enable enforcement of the security policies.
    Type: Application
    Filed: April 2, 2024
    Publication date: November 28, 2024
    Applicant: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Eli Boling
  • Publication number: 20240354412
    Abstract: Systems and methods for on-demand loading of metadata. In some embodiments, in response to receiving a page fault service request from an operating system kernel, at least one first physical page may be allocated in an application memory for a virtual address indicated in the page fault service request. Metadata may be loaded into at least one second physical page in a metadata memory, wherein: the at least one second physical page in the metadata memory corresponds to the at least one first physical page in the application memory; and the metadata loaded into the at least one second physical page corresponds to application data loaded into the at least one first physical page.
    Type: Application
    Filed: September 2, 2022
    Publication date: October 24, 2024
    Applicant: DOVER MICROSYSTEMS, INC.
    Inventors: Eli Boling, Steven Milburn
  • Patent number: 12124576
    Abstract: Systems and methods for violation processing. In some embodiments, in response to detecting a policy violation, tag processing hardware may enter a violation processing mode, and may cause a host processor to begin executing violation processing code. The tag processing hardware may continue checking one or more instructions in an instruction queue. In response to encountering, in the instruction queue, an instruction of the violation processing code, the tag processing hardware may exit the violation processing mode.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: October 22, 2024
    Assignee: Dover Microsystems, Inc.
    Inventors: Eli Boling, Steven Milburn
  • Patent number: 12124566
    Abstract: Systems and methods for metadata processing. In some embodiments, a target address may be received from a host processor. The target address may be used to access mapping information and decoding information, the mapping information and the decoding information being associated with the target address. The mapping information may be used to map the target address to a metadata address. The metadata address may be used to retrieve metadata, and the decoding information may be used to decode the retrieved metadata.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 22, 2024
    Assignee: Dover Microsystems, Inc.
    Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland
  • Publication number: 20240345869
    Abstract: Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor.
    Type: Application
    Filed: December 15, 2023
    Publication date: October 17, 2024
    Applicant: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Gregory T. Sullivan
  • Publication number: 20240296122
    Abstract: Systems and methods for caching metadata. In some embodiments, in response to an access request comprising an application memory address, it may be determined whether the application memory address matches an entry of at least one cache. In response to determining that the application memory address does not match any entry of the at least one cache: the application memory address may be used to retrieve application data; the application memory address may be mapped to at least one metadata memory address; and the at least one metadata memory address may be used to retrieve metadata corresponding to the application memory address. An entry in the at least one cache may be created, wherein: the entry is indexed by the application memory address; and the entry stores both the application data retrieved using the application memory address, and the corresponding metadata retrieved using the at least one metadata memory address.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 5, 2024
    Applicant: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Nirmal Nepal