Abstract: A content addressable memory circuit is provided that includes: multiple integrated circuit memory devices that include memory address locations that share common memory addresses; buffer circuits operatively coupled to the memory devices; a hash table that includes a plurality of hash values that each corresponds to one or more key values; one or more processor circuits configured with instructions to perform operations that include: assigning each hash value to a memory address location based upon a first portion of the hash value; storing each key value at a memory address location assigned to a first portion of a hash value that corresponds to the key value; copying a first key value from a first memory address location within a memory device to a buffer circuit operatively coupled to the memory device; copying the first key value from the buffer circuit operatively coupled to the memory device to a second memory address location of the memory device; and assigning a second portion of a hash value that co

Abstract: A content addressable memory circuit comprising: a memory device array including multiple memory devices coupled for simultaneous access to memory address locations that share a common memory address; multiple virtual modules (VMs), wherein each VM stores a data set that includes key values stored within an assigned memory address range within the memory array that are assigned to the VM; wherein each VM, stores a virtual hash table in non-transitory memory, that associates hash values with memory addresses within an assigned memory address range of the VM; hash logic is operable to determine a hash value, based upon a received key value and a respective assigned memory address range; and memory controller logic is operable to use a virtual hash table to access a memory address in an assigned memory address range, based upon the determined hash value.

Abstract: A method is provided to control a content addressable memory that includes multiple integrated circuit memory devices that include common memory address locations and that are coupled for simultaneous access to the common memory address locations, the method comprising; determining a hash value, based upon a received key value, that corresponds to a common memory address location of the multiple memory devices; providing activity status information for multiple common memory address locations of the memory devices; selecting a memory devices from which to output stored content data from the corresponding common memory address location, based upon storage activity status information; and causing the selected one or more memory devices to output stored content data.

Abstract: A ternary content addressable memory is provided comprising; a memory device that includes a plurality of memory address locations; hash logic operative to determine a hash value, based upon a ternary key, wherein the determined hash value corresponds to a memory address location of the memory device; an encoder operable to convert the ternary key to a binary bit representation; wherein converting includes determining binary mapping bits based upon number and positions of ternary non-X (don't care) value bits of the ternary key; wherein converting further includes determining a different binary data bit to correspond to each different ternary non-X value bit of the ternary key; and memory controller logic to cause the memory device to store the binary bit representation at the memory address location that corresponds to the determined hash value.

Abstract: A NOT logic circuit is provided comprising: one or more memory devices; wherein a first memory address location of the one or more memory devices stores first content data, wherein the first content data includes a first ternary value and a corresponding first priority value, wherein the first ternary value includes a continuous sequence of X-state values that represent a first range of non-X ternary values; wherein a second memory address of the one or more memory device stores second content data that includes a second ternary value and a corresponding second priority value, wherein the second ternary value includes a continuous sequence of non-X state values represent a non-X ternary value that is within the first range of non-X ternary values; an interface is coupled to receive a ternary value from a processing device; comparator circuitry operable to compare a received ternary key with the outputted first ternary value and to compare the received ternary key with the outputted second ternary value; prior