Abstract: Dry plasma etching of a plurality of planar thin-film semiconductor wafers is effected simultaneously and uniformly in a relatively small chamber enveloping a vertically-stacked array of laminar electrode sub-assemblies each of which includes a pair of oppositely-excited electrode plates tightly sandwiching a solid insulating layer of dielectric material, the parallel sub-assemblies being vertically separated to subdivide the chamber into a plurality of reactor regions where RF discharges can excite a normally inert ambient gas to develop reactive plasma for simultaneous planar plasma etching or reactive ion etching (RIE) of all wafers within the several regions.