Abstract: A memory array includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found. In one embodiment useful for neighboring words, the left memory unit holds the words with even addresses and the right memory unit holds the words with odd addresses. In another embodiment, the left memory unit holds the first four words of an eight word set and the right memory unit holds the second four words.

Abstract: A data processing and addressing unit for processing a set of either first or second type instructions having associated therewith operands stored in a single memory bank and operands stored in two memory banks, respectively. First and second memory banks are mapped in continuous memory address space such that a bottom address of the second memory bank is contiguous with a top address of the first memory bank. A method is employed for mapping the first and second memory banks so as to permit memory expansion or contraction while permitting the first and second memory banks to be configured as a single continuous buffer or as two distinct buffers, as required.