Abstract: A system and method of merging and manipulating pixel information for display on a raster scan monitor is disclosed. The invention operates at speeds imperceptible to the viewer by collecting, in each memory access cycle, the data representing multiple pixels and by performing merge and manipulation functions on pixel groups at video rate under control of control data from a state machine. The state machine allows for unique processing decisions to be made for every pixel group displayed on the monitor.
Abstract: A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor.One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus.
March 21, 1989
Date of Patent:
October 8, 1991
Du Pont Pixel Systems Limited
David R. Baldwin, Malcolm E. Wilson, Neil F. Trevett
Abstract: A method of performing an integral transform operation (such as a Fast Fourier Transform), wherein the underlying algorithm is partitioned to provide an efficient sequence of data operations. Preferably the address calculations are performed separately from the data calculations, and the algorithm is partitioned so that the microcode sequence for all but the last few data calculations is constant. Thus, the bandwidth at the interface to the numeric processor is conserved, and control storage in the numeric processor is also efficiently conserved. Moreover, the preferred partition for performing Fast Fourier Transform manipulates data in reasonably large subsets (e.g. 8 floating-point words at a time). This turns out to use less data bandwidth than would be required using smaller data subsets.
Abstract: A system and method for merging two or more analog video signals under control of a third analog video signal. A standard video output from one processor's video signal digital to analog converter (DAC) is used as the control signal for the merging of two or more other video signals. This enables the video outputs of even highly diverse processing schemes to be easily merged. In its preferred embodiment, the system includes analog switching circuitry which is used to mix the video outputs from two or more different systems. The system also includes circuitry which converts the standard video output from a third processor into a large swing TTL signal which is used to control the analog switch.