Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

Abstract: The present invention discloses an asynchronous serial communication system and method. The asynchronous serial communication system may include a semiconductor device having two terminals and configured to receive a voltage required for an operation from data transmitted through one terminal; and a controller configured to perform asynchronous serial communication with the semiconductor device with two terminals. The asynchronous serial communication system may perform asynchronous serial communication between the semiconductor device and the controller in order to write or read data through the one terminal.

Abstract: The present invention discloses an asynchronous serial communication system and method. The asynchronous serial communication system may include a semiconductor device having two terminals and configured to receive a voltage required for an operation from data transmitted through one terminal; and a controller configured to perform asynchronous serial communication with the semiconductor device with two terminals. The asynchronous serial communication system may perform asynchronous serial communication between the semiconductor device and the controller in order to write or read data through the one terminal.