Patents Assigned to DUET MICROELECTRONICS INC.
  • Patent number: 10848106
    Abstract: An automatic gain control (AGC) transimpedance amplifier (TIA) uses a differential structure with feedback PIN diodes to adjust the loop gain of the amplifier automatically to maintain stability over a wide dynamic range when converting optical power using a photodiode to an electrical signal. A stable DC current derived from the photodiode current sets the voltage gain of the amplifier. The use of ultra-linear long carrier lifetime PIN diodes assures the transimpedance feedback resistance is linear. The AGC function adjusts the gain of the TIA to provide a linear stable differential transresistance controlled by the photodiode current; a linear stable AGC function using current supplied by the photodiode; an improvement of about 10 db of the transresistance dynamic range; and reduces the need for internal and external circuitry needed to provide the same function. The TIA is applicable to CATV optical systems which have very strict linearity requirements.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: November 24, 2020
    Assignee: Duet Microelectronics, Inc.
    Inventor: Robert J. Bayruns
  • Patent number: 10566449
    Abstract: The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 18, 2020
    Assignee: Duet Microelectronics, Inc.
    Inventors: John Bayruns, Robert J. Bayruns, Ashok T. Ramu
  • Publication number: 20190267480
    Abstract: A field effect transistor (FET) includes a substrate, a back barrier disposed on the substrate, a channel disposed on the back barrier, a front barrier disposed on the channel, a source, and a drain, such that at least one of the front barrier and the back barrier includes an anti-barrier-conduction (ABC) spacer which reduces parasitic conduction on a path from the source to the drain through at least one of the front barrier and the back barrier, reduces ON-state leakage from the channel to gate or substrate of the FET via resonant tunneling, and reduces OFF-state leakage by presenting tall barriers to electrons as well as electron-holes. This results in a highly linear, low gate leakage, low parasitic conduction, and low noise operation of FET.
    Type: Application
    Filed: January 4, 2019
    Publication date: August 29, 2019
    Applicant: DUET MICROELECTRONICS INC.
    Inventors: Ashok T. Ramu, Keun-Yong Ban
  • Publication number: 20190252243
    Abstract: A structure and manufacturing process produce an airbridge for semiconductor devices and circuit applications. Magnesium oxide (MgO) is used to fabricate airbridges. The use of evaporated MgO allows for a thicker and strong airbridge structure, and increases the yield during the singulation of the fabricated devices and circuits. Using MgO as a sacrificial layer provides the flexibility for the sacrificial layer to be removed during the backend process, thereby avoiding any damage in the airbridge structures. In an alternative embodiment, some or all of the MgO can be retained in the airbridge structure, allowing for high density interconnects especially for ground connected interconnects.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 15, 2019
    Applicant: DUET MICROELECTRONICS INC.
    Inventors: Ali Badar Alamin Dow, John Ueng-McHale, David Osika
  • Publication number: 20190245491
    Abstract: A transmit-receive (T-R) circuit is switchable for both small and large signals using a high impedance low noise amplifier, which lacks T-R switches, and which permits implementation using only bipolar transistors for integration into the fabrication of integrated circuits. The relatively large T-R switch loss is eliminated, resulting in better efficiency in operation of the T-R circuit. When the T-R circuit is in a transmit mode, a power amplifier is in an ON state, and the low noise amplifier is in an OFF state, such that the low noise amplifier has a high impedance between the LNA input and the LNA output to block a first signal from the LNA input from reaching the antenna. When the T-R circuit is in a receive mode, the power amplifier is in an OFF state, and the low noise amplifier is in an ON state with a low impedance.
    Type: Application
    Filed: January 24, 2019
    Publication date: August 8, 2019
    Applicant: DUET MICROELECTRONICS INC.
    Inventor: Robert Bayruns
  • Patent number: 10347738
    Abstract: Fabrication of a dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistor (HEMT) called a threshold control terminal HEMT (TCT-HEMT) is performed which reduces capacitance between the TCT electrode and the source and drain electrodes of a TCT-HEMT, since such a capacitance may be parasitic, and which fabricates a TCT-HEMT capable of high-frequency operation. A method for fabricating a field-effect transistor (FET) includes: providing a substrate; disposing a back barrier on the substrate to form a base stack; forming a doped layer on the base stack; grow additional layers, including a threshold-control terminal (TCT) access layer; etch a pattern in at least one of the doped layer and the additional layers; and disposing a TCT contact on the TCT access layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 9, 2019
    Assignee: Duet Microelectronics, Inc.
    Inventors: Ashok T. Ramu, Keun-Yong Ban, John Bayruns, Robert J. Bayruns
  • Publication number: 20190189580
    Abstract: A method for fabricating an electronic device includes fabricating a plurality of electronic components on a substrate; fabricating a plurality of posts on the plurality of electronic components; depositing filling material between the plurality of posts; and depositing a plurality of top layers, with each top layer disposed on a respective post, thereby fabricating the electronic device. Each top layer is composed of a metal. The step of fabricating the posts includes: fabricating the posts to have identical heights above the substrate. Each post is thermally-conductive, and may be composed of gold. The filling material is composed of MgO, which may be electron beam evaporated to be disposed between the posts. The step of depositing the filling material includes: controlling a thickness of the MgO being deposited by controlling an evaporation rate of the MgO.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 20, 2019
    Applicant: DUET MICROELECTRONICS INC.
    Inventors: Ali Badar Alamin Dow, Robert Bayruns, David Osika, John Ueng-McHale
  • Publication number: 20190109242
    Abstract: A PIN diode has an anode spaced away from a central region of a top surface of a substrate, such that the anode is in a corner or at a side edge of the top surface. Alternatively, the PIN diode has an anode surrounded by a shield layer. The PIN diode reduces unwanted parasitic capacitance to increase the reverse isolation of RF switches and to reduce the diffusion capacitance to increase the f3dB frequency specification of amplifier circuits. The PIN diode dramatically reduces the values of both parasitic and diffusion capacitances, which enables its application in switches and amplifiers under a wide variety of bias conditions including reverse, low-moderate forward, and large forward-bias; which enables bonding to a much larger metal area than the active electrode, with negligible increase in the parasitic capacitance; and which enables reliable wire-bonding by presenting a highly planar metal surface.
    Type: Application
    Filed: August 13, 2018
    Publication date: April 11, 2019
    Applicant: DUET MICROELECTRONICS INC.
    Inventors: Ashok T. Ramu, Robert J. Bayruns, Michel Francois