Abstract: An integrated circuit includes circuitry organized into sub-blocks, and power supply selection circuitry operative to selectively adjust the connectivity of power supply terminals of the sub-blocks. When the integrated circuit is operating in an active mode, the power supply selection circuitry couples the sub-blocks in parallel between upper and lower active-mode power supplies; when the integrated circuit is operating in a standby mode, the power supply selection circuitry couples two or more sub-blocks in series between upper and lower standby-mode power supplies. Additionally, in standby mode, isolation circuitry within a sub-block is activated to isolate circuitry within the sub-block from input or output terminals of the sub-block.

Abstract: Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.

Abstract: A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.

Abstract: A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.

Abstract: The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.

Abstract: The stability of a channel in a wireless network is evaluated at a node. Upon transmitting a packet from the node on a network channel, a first counter associated with the channel is incremented. Upon receiving an acknowledgment packet responsive to the transmitted packet, a second counter associated with the channel is incremented. A stability metric for the channel is computed based on values stored in the first and second counters. Additionally, interference on a channel of the network is measured at a node. Upon determining that no packet is received during a predetermined time-period on the channel, a received signal strength (RSS) is measured on the channel at an end of the predetermined time-period. Alternatively, upon determining that a packet is received during the predetermined time-period on the channel, the RSS is measured on the channel following completion of the transmission of the packet on the channel.

Abstract: A system for determining path stability using source routed packets in a wireless network comprises a processor and a memory. The processor is configured to select a source route on which to send one or more probing packets, wherein the source route includes a path between a first node and a second node and calculate a stability of the path based at least in part on a success or a failure location of each of the one or more probing packets. The memory is coupled to the processor and configured to provide instructions to the processor.

Abstract: A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling.

Abstract: A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling.

Abstract: A precision temperature sensing system includes a heater and a sensing element disposed on a semiconductor substrate. A power source drives the heater on a periodic basis according to a received clock signal. The sensing element senses the heat emitted by the heater and diffused through the semiconductor substrate. Processing circuitry coupled to the sensing element adjusts a phase of the periodic heater driving signal based on the heat sensed by the sensing element. The processing circuitry determines a temperature based on a thermal diffusivity (TD) of the semiconductor substrate, the adjusted value of the phase, and a known distance between the heater and the sensing element. A second temperature sensor can be disposed on the same substrate as the precision temperature sensing system, and calibrated based on temperature measurements obtained while applying a reference frequency signal to the precision sensing system.

Abstract: Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.

Abstract: A system for maintaining synchronization of nodes in a wireless network comprises a child node and a parent node. The child node comprising a transmitter, a receiver, and a first time keeper. The parent node comprising a transmitter, a receiver, a second time keeper. The parent node receiver is active for a guardband and wherein the guardband is adjusted to maintain synchronization of the parent node with the child node.

Abstract: A system for discovering neighbors during wireless network joining comprises a first wireless network node and a second wireless network node. The first wireless network node listens for a message from a third wireless network node based at least in part on information received in a communication form the second wireless network node.

Abstract: A system for determining node locations comprises an interface for receiving a first set of measurements at a first set of nodes, the first set of nodes having known locations. The system further comprising an interface for receiving a second set of measurements at a node having an unknown location, and a processor configured for determining a location of the node with unknown location based at least in part on the first set of measurements and the second set of measurements.

Abstract: Phase noise in a first clock signal is measured using a time to digital converter (TDC) by determining variations in the phase delay between the first clock signal and a second clock signal. The TDC can include first and second series interconnections of delay elements, first and second sets of latches, and processing circuitry coupled to the latches and configured to determine the phase delay. The TDC can include a series interconnection of delay elements, latches, and circuitry configured to selectively adjust the control signal connected to the delay elements based on the output of the latches. The phase noise measurement can be used in a sampling circuit, so as to produce a second data signal from a first data signal based on the first clock signal and the measured phase noise.

Abstract: An integrated circuit includes circuitry organized into sub-blocks, and power supply selection circuitry operative to selectively adjust the connectivity of power supply terminals of the sub-blocks. When the integrated circuit is operating in an active mode, the power supply selection circuitry couples the sub-blocks in parallel between upper and lower active-mode power supplies; when the integrated circuit is operating in a standby mode, the power supply selection circuitry couples two or more sub-blocks in series between upper and lower standby-mode power supplies. Additionally, in standby mode, isolation circuitry within a sub-block is activated to isolate circuitry within the sub-block from input or output terminals of the sub-block.

Abstract: Self managing a low power network is disclosed. A packet is received which includes network information and it is determined if a management action is required based at least in part on information in the packet. In the event that management action is required, the management action is performed wherein the management action is determined based at least in part on information in the packet.

Abstract: A method for processing a source routed packet comprises determining a next node in a source route for a source routed packet in a mesh network and transmitting the source routed packet to the next node in the source route. A method for creating a source routed packet comprises determining a source route path to a destination node and transmitting a source routed packet that includes the source route path to a first node associated with the source route path.

Abstract: Correcting a time of reception of a data packet is disclosed. A radio-frequency input is converted to a data-output signal. A data clock is recovered from the data-output signal. A phase offset is measured between the data-output signal and the data clock. A time of reception is corrected based at least in part on a timestamp. The timestamp is a sampled value of a counter at a time of reception of a data packet and the phase offset. The time correction can be used to calculate a distance estimate.

Abstract: A modulator for modulating a radio frequency signal comprises a voltage controlled oscillator, a first feedback path, and a second feedback path. The first feedback path is coupled between a detector output and the voltage controlled oscillator. The second feedback path is coupled between the detector output and the voltage controlled oscillator. The detector is coupled to a divided down output of the voltage controlled oscillator and a reference clock.