Patents Assigned to DVDO, Incorporated
  • Patent number: 6473476
    Abstract: A clock divider system with reset synchronization includes a divider circuit, a synchronizer circuit, and a synchronous delay circuit. The divider circuit has a clock input, a divider reset input, and a divided clock output. The synchronizer has a clock input, and a synchronous reset input, and a synchronized reset output having an active edge aligned with an active edge of the clock. The synchronous delay circuit has a clock input and a synchronized reset input coupled to the synchronized reset output of the synchronizer, and an output coupled to the divider reset input of the divider.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: October 29, 2002
    Assignee: DVDO, Incorporated
    Inventor: Jano D. Banks