Abstract: A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.
Type:
Grant
Filed:
March 17, 2009
Date of Patent:
December 28, 2010
Assignee:
Dynamic Details, Inc.
Inventors:
Raj Kumar, Monte Dreyer, Michael J. Taylor
Abstract: Methods of manufacturing printed circuit boards having circuit layers laminated with stacked (or staggered) micro via(s). Aspects of embodiments of the present invention are directed to a method of manufacturing a printed circuit board with Z-axis interconnect(s) or micro via(s) that can eliminate a need for plating micro vias and/or eliminate a need for planarizing plated bumps of a surface, that can be fabricated with one or two lamination cycles, and/or that can have carrier-to-carrier (or substrate-to-substrate) attachments with conductive vias, each filled with a conductive material (e.g., with a conductive paste) in the Z-axis. In one embodiment, a printed circuit board having a plurality of circuit layers with at least one z-axis interconnect can be fabricated using a single lamination cycle.
Type:
Grant
Filed:
February 14, 2007
Date of Patent:
April 28, 2009
Assignee:
Dynamic Details, Inc.
Inventors:
Raj Kumar, Monte Dreyer, Michael J. Taylor