Abstract: An integrated circuit includes main power busses located on the next to the top most level of metal and a top level of metal separated from the main power busses by a thin dielectric. The top most level metal is connected to one of the power buses either through bond wires or through contacts. This structure provides a distributed bypass capacitance between the power buses thus stabilizing the power bus voltage within the integrated circuit. Furthermore, this capacitance structure can be optional and can be made with one or two masking steps.
Type:
Grant
Filed:
October 7, 1997
Date of Patent:
November 14, 2000
Assignee:
E. R. W.
Inventors:
Eugene Robert Worley, Richard Arthur Mann