Abstract: A method for producing a wafer interposer (210) for use in a wafer interposer assembly is disclosed. The wafer interposer (210) is produced by attaching solder bumps (140) to a lower surface of a support (120). First electrical terminals (130) are attached to an upper surface of the support (120) and substantially correspond to the solder bumps (140). First electrical pathways are provided that passes through the support (120) and connect the solder bumps (140) to the first electrical terminals (130). Second electrical terminals (310) are attached to the upper surface of the support (120). Second electrical pathways (320) connect the first electrical terminals (130) to the second electrical terminals (310).

Abstract: A wafer-interposer assembly (10) includes a semiconductor wafer (12) having a plurality of semiconductor die (14) that have a plurality of first electrical contact pads (16). An interposer (22) is connected to the semiconductor wafer (12) such that a plurality of second electrical contact pads (26) associated with the interposer (22) are respectively connected to at least some of the first electrical contact pads (16) via conductive attachment elements (20). A communication interface (28) is integrally associated with the interposer (22) and electrically connected to at least some of the plurality of second electrical contact pads (26). The interposer (22) and the semiconductor wafer (12) are operable to be singulated into a plurality of chip assemblies.

Abstract: A wafer interposer assembly and a system for building the same are disclosed. The wafer interposer assembly includes a semiconductor wafer (10) having a die (11) and a redistribution layer pad (13) electrically connected to the die (11). An epoxy layer (20) is deposited on the surface of the redistribution layer pad (13) and the die (11). An interposer pad (50) is positioned in an opening (40) in the epoxy layer (20) in electrical contact with the redistribution layer pad (13).

Abstract: A system for testing semiconductor die on multiple semiconductor wafers includes a testing unit (82), a test fixture bank (84) operably coupled to the testing unit (82), a plurality of test fixture racks (86-92) operably coupled to the test fixture bank (84) and a plurality of wafer-interposer assemblies (94-140) operably coupled to each of the test fixture racks (86-92). Each of the wafer-interposer assemblies (94-140) includes a semiconductor wafer having a plurality of semiconductor die and an interposer coupled to the semiconductor wafer. The interposer has a first set of conductors for electrically connecting the semiconductor die of the semiconductor wafer to a substrate and a second set of conductors that electrically connect the semiconductor die of the semiconductor wafer to the test fixture rack (86-92) via a connector, thereby providing for addressing and testing of the semiconductor die.

Abstract: A method for reducing the likelihood of damaging a semiconductor wafer (18) and the integrated circuit chips of the semiconductor wafer (18) during handling utilizes a wafer interposer (12) having a wafer receiving portion (28) and a handling portion (30). The wafer receiving portion (28) of the wafer interposer (12) has a plurality of contact pads (22) that are electrically and non-temporarily mechanically connected to the contact pads of the integrated circuit chips of the wafer (18). The handling portion (30) of the wafer interposer (12) extends outwardly from the wafer receiving portion (28) such that the handling portion (30) is accessible to handling equipment without the handling equipment contacting the attached wafer (18).

Abstract: An apparatus and method for manufacture and testing of semiconductor chips (14) is disclosed. The invention comprises the use of an interposer (22) having a plurality of electrical contact pads (26) on each surface connected by a plurality of conductors (32, 34). After assembly of the interposer (22) to a semiconductor wafer (12), the wafer-interposer assembly (10) is attached to a testing unit (46) wherein the semiconductor chips (14) on the wafer (12) are tested. After testing, the interposer-wafer assembly (10) is singulated into a plurality of chip assemblies (62), each chip assembly (62) comprising a silicon chip (64) and the permanently attached interposer (66).

Abstract: The present invention provides a system, method and apparatus for testing multiple semiconductor wafers. The method includes the steps of attaching two or more wafer-interposer assemblies to a testing apparatus and testing each semiconductor die. Each wafer-interposer assembly comprises an interposer connected to one of the semiconductor wafers and each semiconductor wafer includes one or more semiconductor die. The present invention also provides a test fixture rack having a test fixture backbone, two or more wafer-interposer connectors attached to the test fixture backbone, and one or more connectors attached to the test fixture backbone and electrically coupled to the two or more wafer-interposer connectors such that each semiconductor die can be addressed and tested using the one or more connectors. Each wafer-interposer connector is designed to receive a wafer-interposer assembly having an interposer connected to one of the semiconductor wafers.

Abstract: A matched set of integrated circuit chips (24) and a method for assembling such integrated circuit chips (24) into a matched set are disclosed. A semiconductor wafer (18) having a plurality of integrated circuit chips (24) is electrically and mechanically coupled to a wafer interposer (12) to form a wafer-interposer assembly (10). The integrated circuit chips (24) of the wafer (18) are then tested together by attaching the wafer-interposer assembly (10) to a testing apparatus and running the integrated circuit chips (24) through various testing sequences. The wafer-interposer assembly (10) is then diced into a plurality of chip assemblies each having a chip (24) and a section of the wafer interposer (12). Based upon the testing, the chip assemblies are sorted and at least two of the chip assemblies are selected for inclusion in the matched set.

Abstract: The present invention provides a wafer-interposer assembly apparatus and method. The method for manufacturing the wafer-interposer assembly including the steps of providing a semiconductor wafer and an interposer. The semiconductor wafer including one or more semiconductor die, each semiconductor die having one or more first electrical contact pads. The interposer having one or more communication interfaces and a second electrical contact pad corresponding to each of the one or more first electrical contact pads on each semiconductor die of the semiconductor wafer, and at least one of the second electrical contact pads electrically connected to the one or more communication interfaces. The wafer-interposer assembly is formed by connecting each first electrical contact pad of the semiconductor wafer to the corresponding second electrical contact pad of the interposer with a conductive attachment element.

Abstract: A matched set of integrated circuit chips (34, 38) includes a chip (34) from a first wafer (22) and a chip (38) from a second wafer (24). The chips (34, 38) of the first and second wafers (22, 24) are tested together as part of a wafer-interposer assembly (10). The matched set comprises a first chip assembly diced from the wafer-interposer assembly (10) having one of the chips (34) from the first wafer (22) and a second chip assembly diced from the wafer-interposer assembly (10) having one of the chips (38) from the second wafer (24). A substrate is electrically coupled to the first and second chip assemblies, the first and second chip assemblies being selected for the matched set based upon sorting of the chips (34, 38) of the first and second wafers (22, 24) as a result of the testing.

Abstract: An apparatus (10) for reducing the likelihood of damaging a semiconductor wafer (18) and the integrated circuit chips of the semiconductor wafer (18) during handling is disclosed. The apparatus (10) comprises a wafer interposer (12) having a wafer receiving portion (28) and a handling portion (30). The wafer receiving portion (28) of the wafer interposer (12) has a plurality of contact pads (22) that are electrically connected and mechanically bonded to the contact pads of the integrated circuit chips of the wafer (18). The handling portion (30) of the wafer interposer (12) extends outwardly from the wafer receiving portion (28) such that the handling portion (30) is accessible to handling equipment without the handling equipment contacting the attached wafer (18).

Abstract: The present invention provides a method and apparatus for testing semiconductor wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. After testing, the wafer is diced into the individual circuits, eliminating the need for additional packaging. One form of the present invention provides an interposer substrate made of a ceramic material that has an upper and a lower surface. There are one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. There are also one or more electrical pathways that connect the first and second electrical contacts.

Abstract: A matched set of integrated circuit chips (74, 78) and a method for assembling such integrated circuit chips (74, 78) into a matched set are disclosed. A first semiconductor wafer (62) having a plurality of integrated circuit chips (74) of a first type and a second semiconductor wafer (64) having a plurality of integrated circuit chips (78) of a second type are electrically and mechanically coupled to an interposer (52) to form a wafer-interposer assembly (50). The integrated circuit chips (74, 78) of the first and second wafers (62, 64) are then tested together. The wafer-interposer assembly (52) is then diced into a plurality of chip assemblies having chips (74) of the first type and a plurality of chip assemblies having chips (78) of the second type. Based upon the testing, at least one of the chip assemblies having chips (74) of the first type and at least one of the chip assemblies having chips (78) of the second type are selected for inclusion in the matched set.

Abstract: The present invention provides a method, apparatus and system for building a wafer-interposer assembly. The method includes the steps of forming a redistribution layer (RDL) pad on a semiconductor wafer. The semiconductor wafer has a semiconductor die and the RDL pad has an electrical connection to the semiconductor die. A layer of epoxy is placed on the semiconductor wafer and on the RDL pad. The epoxy is then leveled generally parallel to the surface of the semiconductor wafer and removed from a portion of the RDL pad. An interposer pad is formed on the RDL pad where the epoxy was removed.

Abstract: A chip assembly (162) with integrated power distribution between an integrated circuit chip (164) and a section of wafer interposer (166) is disclosed. The wafer interposer section (166) has first (80, 82) and second (86, 88) sets of contact pads that are electrically and mechanically coupled to first and second sets of contact pads of the integrated circuit chip (164). The wafer interposer section (166) has first (32) and second (36) supply voltage terminals that are respectively coupled to the first (80, 82) and second (86, 88) sets of contact pads of the wafer interposer section (166) that provide first and second supply voltages to the first and second sets of contact pads of the integrated circuit chip (164), thereby integrating power distribution between the integrated circuit chip (164) and the wafer interposer section (166).

Abstract: A matched set of integrated circuit chips (74, 78) and a method for assembling such integrated circuit chips (74, 78) into a matched set are disclosed. A first semiconductor wafer (62) having a plurality of integrated circuit chips (74) of a first type and a second semiconductor wafer (64) having a plurality of integrated circuit chips (78) of a second type are electrically and mechanically coupled to a pair of interposers (52, 53) to form a pair of wafer-interposer assemblies (50, 51). The integrated circuit chips (74, 78) of the first and second wafers (62, 64) are then tested together. The wafer-interposer assemblies (52, 53) are then diced into a plurality of chip assemblies having chips (74) of the first type and a plurality of chip assemblies having chips (78) of the second type. Based upon the testing, at least one of the chip assemblies having chips (74) of the first type and at least one of the chip assemblies having chips (78) of the second type are selected for inclusion in the matched set.

Abstract: The present invention provides a method and apparatus for testing wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. The invention also provides for packaging of the die at the completion of testing. One form of the present invention provides an interposer substrate connected to a wafer through conductive columns.

Abstract: An apparatus and method for manufacture and testing of semiconductor chips (14) is disclosed. The invention comprises the use of an interposer (22) having a plurality of electrical contact pads (26) on each surface connected by a plurality of conductors (32, 34). After assembly of the interposer (22) to a semiconductor wafer (12), the wafer-interposer assembly (10) is attached to a testing unit (46) wherein the semiconductor chips (14) on the wafer (12) are tested. After testing, the interposer-wafer assembly (10) is singulated into a plurality of chip assemblies (62), each chip assembly (62) comprising a silicon chip (64) and the permanently attached interposer (66).