Patents Assigned to Ecchandes INC
  • Patent number: 7664220
    Abstract: An interlocked counter including a synchronous counter, a logic gate for judging end-value, a logic gate for amplifying an interlocking signal, at least one latch circuit for the interlocking signal, a logic gate for the interlocking signal, and a logic gate for an enable signal, wherein behavior of the synchronous counter is stopped when a count number arrived at an end value, by that the synchronous counter counts a number of pulses of a clock signal when the synchronous counter inputted an enable signal, the logic gate for judging end-value generates an interlocking signal when the count number outputted by a synchronous counter coincided with the end value, the logic gate for amplifying interlocking signal amplifies the interlocking signal in order to output to an external part, and the logic gate for enable signal generates the enable signal when the interlocking signal is not generated.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: February 16, 2010
    Assignee: Ecchandes Inc.
    Inventor: Yoshiaki Ajioka
  • Patent number: 7396168
    Abstract: A first guide rail (11), and a second guide rail (12) and a third guide rail (13) that are parallel to each other are installed on a base (2) so as to be perpendicular to each other, and these guide rails are rotated about shafts (4) installed on both ends. When the guide rails are rotated, an indication bar (3) installed on a rotor (1) is moved synchronously with the movement of the guide rails, so that the rotor (1) is also rotated. A slider (22) installed on the indication bar (3) slides along a slit (21) of the third guide rail (13). Then a rotation angle of the rotor (1) about the indication bar (3) is determined by the distance between the guide rails.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: July 8, 2008
    Assignee: Ecchandes Inc.
    Inventor: Yoshiaki Ajioka
  • Publication number: 20080025567
    Abstract: A visual device including plurality of array operation units or plurality of virtual array operation units arranged in a shape of a two-dimensional lattice, wherein each of all of the array operation units and all of the virtual array operation units includes a processor, a set of memories and plurality of controllers, wherein at least one controller transmits a calculation datum only at most a number of times related to a number of the controller, to which the processor wrote the calculation data, by that a number is assigned to at least two controllers at intervals of an appointed number, and each of all of the controllers based on a number shifting arrangement.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 31, 2008
    Applicant: ECCHANDES INC.
    Inventor: Yoshiaki AJIOKA
  • Publication number: 20080024667
    Abstract: An image sensor including plurality of sensor modules, each of at least one of which includes: plurality of pixel cells arranged in a shape of a two-dimensional lattice; a vertical shift register; a horizontal shift register; plurality of row selection gates; plurality of noise cancellers; and an output amplifier, the noise canceller reduces noise of the voltage outputted via at least one column selection gate, an output of the horizontal shift register make at least one row selection gate conduct; and the output amplifier amplifies an output of the noise cancellor outputted via at least one row selection gate, in each of the sensor modules.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 31, 2008
    Applicant: ECCHANDES INC.
    Inventor: Yoshiaki AJIOKA
  • Publication number: 20080024639
    Abstract: An interlocked counter including a synchronous counter, a logic gate for judging end-value, a logic gate for amplifying an interlocking signal, at least one latch circuit for the interlocking signal, a logic gate for the interlocking signal, and a logic gate for an enable signal, wherein behavior of the synchronous counter is stopped when a count number arrived at an end value, by that the synchronous counter counts a number of pulses of a clock signal when the synchronous counter inputted an enable signal, the logic gate for judging end-value generates an interlocking signal when the count number outputted by a synchronous counter coincided with the end value, the logic gate for amplifying interlocking signal amplifies the interlocking signal in order to output to an external part, and the logic gate for enable signal generates the enable signal when the interlocking signal is not generated.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 31, 2008
    Applicant: ECCHANDES INC.
    Inventor: Yoshiaki AJIOKA
  • Publication number: 20080025593
    Abstract: A visual device including plurality of array operation units arranged in a shape of a two-dimensional lattice, wherein each of the calculation data in each of the array operation units is transmitted counter-clockwisely between plurality of the array operation units arranged in a shape of a two-dimensional lattice.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 31, 2008
    Applicant: ECCHANDES INC.
    Inventor: Yoshiaki AJIOKA
  • Patent number: 6870306
    Abstract: Piezoelectric elements (1) are overlapping on a stator (11) in the same direction as shown in FIG. 3. Since a fixed end (6) of a piezoelectric element (1) is fixed to a foundation (4), an open end (7) of the piezoelectric element (1) elongates in the direction opposite to the foundation (4) when a voltage is applied to the piezoelectric element (1). When a drive device (12) generates a saw-tooth wave shown in FIG. 4(a), the piezoelectric element (1) rapidly elongates or slowly shrinks. A slider (21) then moves while being flicked away by the piezoelectric element (1). On the other hand, since piezoelectric element (1) rapidly shrinks or slowly elongates in the case of FIG. 4(b), a slider (21) moves while being pulled in by the piezoelectric element (1). Because of piezoelectric elements (1) arranged in a circle as shown in FIG. 13, a stator (11) can rotate a circular rotor (31) and a spherical rotor (35).
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: March 22, 2005
    Assignee: Ecchandes Inc.
    Inventor: Yoshiaki Ajioka
  • Patent number: 6856696
    Abstract: A visual device searches for moving and still objects and counts the moving and still objects. The visual device includes a vibrator for vibrating a frame image by using an array calculating unit, an information unit for creating edge information on the moving and still objects from the frame image, a separator for separating the object region of the moving and still objects from the background of the frame image, a measuring unit for measuring the positions and sizes of the moving and still objects, a normalizer for normalizing the separation object regions segmented by the object regions, and a recognition unit for recognizing the normalized regions.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: February 15, 2005
    Assignee: Ecchandes INC
    Inventor: Yoshiaki Ajioka
  • Patent number: D520036
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: May 2, 2006
    Assignee: Ecchandes, Inc.
    Inventor: Yoshiaki Ajioka