Patents Assigned to ECOLE NATIONALE D'INGENIEURS DE TARBES
  • Patent number: 10847494
    Abstract: Some embodiments are directed to a method of determining a sintering thermal impedance of a sintering layer by: providing a substrate having a predetermined substrate thermal impedance and disposing the sintering layer on the substrate forming with the sintering layer a stack. Placing at least one semiconductor die, that includes a semiconductor element with at least two element electrodes on the sintering layer. Injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element. Heating the stack with a predetermined heat power and determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 24, 2020
    Assignees: AGILE POWER SWITCH 3D-INTEGRATION APSI3D, IRT SAINT EXUPERY (AESE), ECOLE NATIONALE D'INGENIEURS DE TARBES
    Inventors: Jacques Pierre Henri Favre, Jean-Michel Francis Reynes, Raphaƫl Riva, Paul-Etienne Joseph Vidal, Baptiste Louis Jean Trajin