Abstract: An embodiment of the present invention relates to a method and apparatus for correcting errors in stereo images. The apparatus for correcting errors in stereo images according to an embodiment of the present invention comprises: a space histogram generation unit generating space histogram information using the depth map information on the input image data; a peak frequency generation unit generating a peak frequency using the 2D image data of the input image data; an object analysis unit determining the error in each frame of the input image data on the basis of the space histogram and peak frequency; a depth map error correction unit correcting the depth map information to reduce the error; and a rendering processing unit generating left and right eye images, which are stereo images, by using the corrected depth map information.

Abstract: An image compression apparatus is provided, which includes a wavelet transformer, a quantizer, a comparator, a subtracter, a low data compressor and a high data compressor. The comparator compares the first quantization coefficients of the first quantization data, to output the maximum quantization coefficient. The subtracter subtracts the minimum quantization coefficient from the maximum quantization coefficient, to output a subtraction constant. The low data compressor subtracts the subtraction constant from the first quantization coefficients, to output low compression data obtained by compressing the first quantization data.

Abstract: A memory testing method for providing test patterns for a memory device is provided. First, the memory is divided into a plurality of blocks and a test pattern is applied to completely test a first block. Next, the first block is filled with all `1`, and other blocks are filled with all `0`. Then, the first block is walked through the entire memory device to quickly test the memory and the function of the address decoder. The invention provides an efficient method for quickly and completely testing the semiconductor memory as well as detecting and locating all the address decoder faults. A method for selecting an optimal number for dividing a memory device into blocks is also presented to minimize the required test time.