Abstract: Low-Density Parity-Check (LDPC) data decoding using iteration-variable accuracy is performed by segmenting a LDPC encoded data block of probability values by dividing the LDPC encoded data block into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the LDPC encoded data block representing a likelihood between binary values, decoding the LDPC encoded data block by adjusting, according to an iteration-variable accuracy parameter, the probability values of the LDPC encoded data block based on a parity-check matrix, the parity-check matrix defining correspondence among data probability value segments and parity probability value segments, and concatenating likely binary values that satisfy the parity-check matrix associated with the probability values of each data probability value segment to form a decoded data block. The iteration-variable accuracy parameter represents a tradeoff between accuracy and computational efficiency.

Abstract: Integrated circuit data stream processing utilizing paged buffering is performed by an integrated circuit that includes an upstream random access memory, a local read counter, a downstream random access memory, a local write counter, and a processor. The local read counter is configured to store a value indicating whether any accessible blocks of data are stored in the upstream memory. The local write counter is configured to store a value indicating whether any downstream pages of the downstream memory are available for recording. The processor is configured to adjust the local read counter to indicate a page release, adjust the local write counter to indicate a page occupy, read a first block of data recorded to the upstream memory, process the first block of data to produce a second block of data, and record the second block of data to the downstream memory.

Abstract: Neural network hardware acceleration data parallelism is performed by an integrated circuit including a plurality of memory banks, each memory bank among the plurality of memory banks configured to store values and to transmit stored values, a plurality of computation units, each computation unit among the plurality of computation units including one of a channel pipeline and a multiply-and-accumulate (MAC) element configured to perform a mathematical operation on an input data value and a weight value to produce a resultant data value, and a computation controller configured to cause a value transmission to be received by more than one computation unit or memory bank.

Abstract: Sequence partition based schedule optimization is performed by generating a sequence and a schedule based on the sequence, dividing the sequence into a plurality of sequence partitions based on the schedule and the data dependency graph, each sequence partition including a portion of the plurality of instructions and a portion of the plurality of buffers, performing, for each sequence partition, a plurality of partition optimizing iterations, and merging the plurality of sequence partitions to produce a merged schedule.

Abstract: Neural network inference may be performed by configuration of a device including an accumulation memory, a plurality of convolution modules configured to perform mathematical operations on input values, a plurality of adder modules configured to sum values output from the plurality of convolution modules, and a plurality of convolution output interconnects connecting the plurality of convolution modules, the plurality of adder modules, and the accumulation memory. The accumulation memory is an accumulation memory allocation of a writable memory block having a reconfigurable bank width, and each bank of the accumulation memory allocation is a virtual combination of consecutive banks of the writable memory block.