Abstract: Disclosed are an insulated gate bipolar transistor and a manufacturing method thereof, an electronic apparatus, and a storage medium. In the insulated gate bipolar transistor manufactured by the method for manufacturing the insulated gate bipolar transistor, a structure sequentially includes a second metal layer, an oxide layer, an epitaxial layer and a first metal layer. A manufacturing process is simple, and the insulated gate bipolar transistor is manufactured into a vertical structure, which not only can reduce a leakage current of an insulated gate bipolar transistor, improving reliability of an insulated gate bipolar transistor, but also solves a problem of an insufficient withstand voltage of a lateral insulated gate bipolar transistor, improving user experience.

Abstract: Disclosed are an insulated gate bipolar transistor and a manufacturing method thereof, an electronic apparatus, and a storage medium. In the insulated gate bipolar transistor manufactured by the method for manufacturing the insulated gate bipolar transistor, a structure sequentially includes a second metal layer, an oxide layer, an epitaxial layer and a first metal layer, a manufacturing process is simple, and the insulated gate bipolar transistor is manufactured into a vertical structure, which not only can reduce a leakage current of an insulated gate bipolar transistor, improving reliability of an insulated gate bipolar transistor, but also solves a problem of an insufficient withstand voltage of a lateral insulated gate bipolar transistor, improving user experience.

Abstract: Disclosed are a cell structure of a semiconductor device, a preparation method thereof and a semiconductor device. The cell structure includes: a substrate of a first conductive type; at least one first trench gate, at least one second trench gate, at least one third trench gate, and at least one fourth trench gate that are sequentially disposed side by side in an upper surface of the substrate; a source region of the first conductive type located in an upper surface of the well region and disposed on two sides of each trench gate; and an emitter metal layer located above the substrate and electrically connected to the source region, where the first trench gate, the second trench gate, and the third trench gate are isolated from the emitter metal layer by a first interlayer dielectric layer, and the fourth trench gate is electrically connected to the emitter metal layer.