Abstract: A multiple mode xDSL interface (60) is disclosed. The multiple mode xDSL interface (60) includes an xDSL termination unit (62) operable to couple to an XDSL link (64) and to manage communication of data across an xDSL physical layer. The mulitple mode xDSL interface (60) also includes a customer premises equipment (CPE) termination unit (65) coupled to the xDSL termination unit (62) and operable to couple to customer premises equipment. The CPE termination unit (65) has an operating mode selected from a plurality of operating modes where each operating mode is associated with a data protocol and supports communication of data across the xDSL physical layer using the associated data protocol.

Abstract: This invention provides a system for transparently mapping user level non-asynchronous transfer mode (ATM) sockets to an ATM virtual channel circuit associated with an operating system of a computer workstation and includes an ATM middleware subsystem for receiving a plurality of ATM extension calls from a non-ATM aware application and translating the plurality of ATM extension calls to a plurality of native ATM API calls. A configuration data base stores translation data for translating the ATM extension calls from the non-ATM application to the native ATM API calls. A WinSocket.TM. application receives the native ATM API calls from the ATM middleware subsystem and responsively generates signals for controlling the operating system according to the contents of the native ATM API calls. The ATM middleware system further generates formatted calls to the operating system from the plurality of ATM extension calls according to preexisting protocols associated with the operating system.

Abstract: A modem operable to communicate information from a communications link to a host using a universal serial bus includes a modem memory operable to store a plurality of ATM cells. The modem also includes a receive manager operable to receive a plurality of ATM cells from the communications link and to store the ATM cell in the modem memory. The receive manager further operates to format the ATM cells into universal serial bus packets, and to transmit each universal serial bus packet to the host as soon as the packet is full. The modem further includes a short packet instigator operable to determine whether each ATM cell contains a termination condition associated with the content of the ATM cell, and in response to determining that an ATM cell contains a termination condition, to instigate transmission of a short packet comprising a universal serial bus packet carrying less than its capacity.

Abstract: A transmit scheduler and method of operation are provided for an asynchronous transfer mode network. The transmit scheduler is operable to write data to and read data from a scheduler table and a virtual channel identifier ("VCI") table in order to schedule cells for virtual channels. The transmit scheduler calculates a location in the scheduler table in which to schedule a cell for a current virtual channel and determines whether a cell for a prior virtual channel is scheduled in the calculated location in the scheduler table. The transmit scheduler then schedules the cell for the current virtual channel at the calculated location in the scheduler table. If a cell for a prior virtual channel was scheduled in the calculated location in the scheduler table, the transmit scheduler writes a pointer into a next pointer field of a record for the current virtual channel in the VCI table, where the pointer provides a link to a record for the prior virtual channel in the VCI table.

Abstract: An ATM adapter for desktop applications includes an adapter for interfacing an ATM network. The adapter includes an ATM application specific integrated circuit (ASIC). The ATM ASIC may interface with a data bus such as an SBus using a host interface circuit. The host interface circuit includes a bus interface, a DMA controller and a slave access controller. The DMA controller controls DMA operations within the ATM ASIC and associates with a RAM interface arbiter. The slave access controller controls operation of an interrupt circuit that goes to the SBus as well as a statistics circuit. The RAM interface arbiter arbitrates communication between the DMA controller, the slave access control circuit, a segmentation engine, and a reassembly engine. The RAM interface arbiter communicates with the RAM bus to a RAM associated with an adapter. The segmentation engine segments data into ATM format for transfer through a physical interface circuit.