Abstract: The present invention relates to neural network accelerator (103) in a field programmable gate array (FPGA) which is based on custom instruction interface of an embedded processor in said FPGA and AXI master interface for DMA purposes, wherein said neural network accelerator (103) comprises of a command control block (301), at least one neural network layer accelerator (303), a response control block (305) and an AXI control block (307). The amount of neural network layer accelerators (103) that can be implemented can be configured easily (such as adding a new type of layer accelerator (303) to said neural network layer accelerator (103)) in said FPGA, which makes said invention flexible and scalable.

Abstract: A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.

Abstract: Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.

Abstract: Methods and apparatuses to provide FPGA neighbor output mux direct connections to reduce, and potentially minimize, routing hops are described. Embodiments described herein include the addition of direct connections from one tile to the output muxing of a neighboring tile. An FPGA apparatus includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of output multiplexors (muxes) of one or more neighboring logic block tiles. The one or more direct connections are configured to drive one or more wires that start at the one or more neighboring logic block tiles.

Abstract: Methods and apparatuses to provide FPGA inter-tile control signal sharing are described. In one embodiment, the FPGA inter-tile muxing for control signals is added in a separate tile. In another embodiment, the control signal muxing is distributed among FPGA tiles and shared using a cascaded configuration.

Abstract: A field programmable gate array (FPGA) has non-highway wire segments for connection to logic blocks, and highway wire segments in a highway network of highways. Each highway has sets of highway wire segments in successive connection. Each successive connection is through a multiplexer. Multiplexers of highways have on-ramps, off-ramps, or both, for programmable connection to wire segments in accordance with programming the FPGA.

Abstract: Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.

Abstract: A system having design tools and methods for using the same in designing an integrated circuit (IC) are described.

Abstract: A digital signal processing block has a first input port, a second input port, a third input port, a cascade input port and an output port. The DSP block may have a cascade output port. The DSP block may have a multiplexer that has selectable output, to the cascade output port, of concatenated inputs from the first input port, the second input port and the third input port. The DSP block may be connectable to another DSP block via a cascade path. The DSP block may have a variable shifter. The DSP block may have a full-width adder and reduced-width input ports.

Abstract: A system having design tools and methods using the same design tools in designing an integrated circuit (IC) are described.

Abstract: A method and apparatus is disclosed herein for segmented and direct routing in a programmable gate array. In one embodiment, the programmable gate array comprises a plurality of programmable tiles, including at least one SHLRT having: a block configurable as a logic function or a routing function; and one or more switching blocks coupled to programmable tiles in the plurality of programmable tiles for segmented routing.

Abstract: A method and apparatus is disclosed herein for segmented and direct routing in a programmable gate array. In one embodiment, the programmable gate array comprises a plurality of programmable tiles, including at least one SHLRT having: a block configurable as a logic function or a routing function; and one or more switching blocks coupled to programmable tiles in the plurality of programmable tiles for segmented routing.

Abstract: An apparatus is disclosed herein for a programmable gate architecture with hybrid logic/routing circuitry. In one embodiment, a programmable gate array comprises a plurality of hybrid logic or routing tiles (HLRT), each of the HLRTs having a hybrid logic-or-routing function (HLR) that is configurable as a logic function or a routing function.