Abstract: The invention provides multicast communication using distributed topologies in a network. The control nodes in the network build a distributed topology of processor nodes for providing multicast packet distribution. Multiple processor nodes in the network participate in the decisions regarding the forwarding of multicast packets as opposed to multicast communications being centralized in the control nodes.

Abstract: A system, method, and adapter for creating fault-tolerant communication busses from standard components, are described. Fault-tolerant interface logic is provided for transmitting and receiving system health and system management signals to and from a module that is designed to be connected to a single RS-485 bus. The fault-tolerant interface logic enables the module to selectively communicate via at least two redundant half-duplex, multipoint, differential RS-485 busses. The fault-tolerant interface logic includes a first RS-485 transceiver connected to a first RS-485 bus, a second RS-485 transceiver connected to a second RS-485 bus, selector logic responsive to a control signal for selecting one of the first and the second busses to receive signals from and for transmitting the received signals to the module, and software logic executable on a baseboard management controller (BMC) chip.

Abstract: A method and system of emulating serial com port communication. A computer processing system has computer-executable operating system instructions including first instructions that interact with a first serial device according to a predefined input/output (I/O) hardware interface. A first serial device has a receive port and a transmit port and has the predefined (I/O) hardware interface. A second serial device has a receive port and a transmit port. The transmit port of the first serial device is in serial communication with the receive port of the second serial device, and the receive port of the first serial device is in serial communication with the transmit port of the second serial device. Computer-executable instructions emulate serial communication port device communication and include instructions that transmit information over another medium in response to receive requests from the second serial device.

Abstract: A method of and a system for autonomously identifying which node in a two-node system has failed are described. The system includes two nodes and a fault-tolerant communication fabric. The fabric defines a plurality of communication paths connecting the two nodes, and fault-tolerant loop-back communication in which each node can send a message to itself utilizing at least one switch structure of the fabric. In addition, each of the two nodes includes logic for performing the service; logic for testing the functionality of the respective node; logic for sending test result messages to both nodes; fault-isolation logic for analyzing test result messages from both nodes; and logic for disabling the other node from performing the service only if the fault-isolation logic determines that the respective node is capable of successfully performing the service and also determines that the other node is incapable of successfully performing the service.

Abstract: Methods and systems for deploying a processing resource in a configurable platform are described. A methods includes providing a specification that describes a configuration of a processing area network, the specification including (i) a number of processors for the processing area network (ii) a local area network topology defining interconnectivity and switching functionality among the specified processors of the processing area network, and (iii) a storage space for the processing area network. The specification further includes processing resource specific persistent settings. The method further includes allocating resources from the configurable platform to satisfy deployment of the specification, programming interconnectivity between the allocated resources and processing resources to satisfy the specification, and deploying the specification to a processing resource within the configurable deployment platform in response to software commands.

Abstract: A method of and a system for autonomously identifying which node in a two-node system has failed are described. The system includes two nodes and a fault-tolerant communication fabric. The fabric defines a plurality of communication paths connecting the two nodes, and fault-tolerant loop-back communication in which each node can send a message to itself utilizing at least one switch structure of the fabric. In addition, each of the two nodes includes logic for performing the service; logic for testing the functionality of the respective node; logic for sending test result messages to both nodes; fault-isolation logic for analyzing test result messages from both nodes; and logic for disabling the other node from performing the service only if the fault-isolation logic determines that the respective node is capable of successfully performing the service and also determines that the other node is incapable of successfully performing the service.

Abstract: A system, method, and adapter for creating fault-tolerant communication busses from standard components, are described. Fault-tolerant interface logic is provided for transmitting and receiving system health and system management signals to and from a module that is designed to be connected to a single RS-485 bus. The fault-tolerant interface logic enables the module to selectively communicate via at least two redundant half-duplex, multipoint, differential RS-485 busses. The fault-tolerant interface logic includes a first RS-485 transceiver connected to a first RS-485 bus, a second RS-485 transceiver connected to a second RS-485 bus, selector logic responsive to a control signal for selecting one of the first and the second busses to receive signals from and for transmitting the received signals to the module, and software logic executable on a baseboard management controller (BMC) chip.

Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.

Abstract: A system and method for disaster recovery for processing resources using configurable deployment platform. A primary site has a configuration of processing resources. A specification of the configuration of processing resources of the primary site is generated. The specification is provided to a fail-over site that has a configurable processing platform capable of deploying processing area networks in response to software commands. Using the specification, software commands are generated to the configurable platform to deploy processing area network corresponding to the specifications.

Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

Abstract: A method and system of emulating serial com port communication. A computer processing system has computer-executable operating system instructions including first instructions that interact with a first serial device according to a predefined input/output (I/O) hardware interface. A first serial device has a receive port and a transmit port and has the predefined (I/O) hardware interface. A second serial device has a receive port and a transmit port. The transmit port of the first serial device is in serial communication with the receive port of the second serial device, and the receive port of the first serial device is in serial communication with the transmit port of the second serial device. Computer-executable instructions emulate serial communication port device communication and include instructions that transmit information over another medium in response to receive requests from the second serial device.

Abstract: A system and method for disaster recovery for processing resources using configurable deployment platform. A primary site has a configuration of processing resources. A specification of the configuration of processing resources of the primary site is generated. The specification is provided to a fail-over site that has a configurable processing platform capable of deploying processing area networks in response to software commands. Using the specification, software commands are generated to the configurable platform to deploy processing area network corresponding to the specifications.

Abstract: A system and method for disaster recovery for processing resources using configurable deployment platform. A primary site has a configuration of processing resources. A specification of the configuration of processing resources of the primary site is generated. The specification is provided to a fail-over site that has a configurable processing platform capable of deploying processing area networks in response to software commands. Using the specification, software commands are generated to the configurable platform to deploy processing area network corresponding to the specifications.

Abstract: A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.

Abstract: The invention provides multicast communication using distributed topologies in a network. The control nodes in the network build a distributed topology of processor nodes for providing multicast packet distribution. Multiple processor nodes in the network participate in the decisions regarding the forwarding of multicast packets as opposed to multicast communications being centralized in the control nodes.

Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.

Abstract: A system and method to virtualize BIOS, including run time services. A processing system has a processor, a memory system with a predefined physical address space, a storage medium, and a communication medium between the processor and the storage medium. The processing system is operable in a pre-execution environment in which a specified portion of the physical address space is used to map basic input/output system (BIOS) run time service routines. The specified portion contains RAM memory. A BIOS virtualization system includes an image of the BIOS processor-executable instructions on the storage medium and processor-executable instructions that retrieve the BIOS image from the storage medium and store the BIOS image into the RAM memory mapped into the second specified portion of physical address space.

Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.

Abstract: A latch mechanism secures a computer component to a chassis; the mechanism includes a base that is attached to the computer component, a latch handle pivotably mounted on the base, the latch handle being capable of pivoting away from the base. An actuator arm is pivotably mounted to the latch handle so that when the latch is pivoted away from the base, the actuator arm will also move away from the base. A cam plate is also pivotably mounted on the base and is capable of rotating with respect to the base. The cam plate includes at least one notch adapted to cooperate with the chassis so that as the cam plate is rotated, the notch selectively engages and disengages with the chassis.

Abstract: The present invention provides chassis for housing at least one processor, the chassis includes at least one compartment adapted to receive a processor, a connector for coupling the at least one processor to the chassis when the processor is installed in the at least one compartment. The connector includes a first component attached to the processor and a second component attached to the chassis and adapted to be mated with the first component, the connector may also be adapted to provide data and power connections between the chassis and the processor when coupled. Additionally, the first component aligns and mates with the second component during the insertion of the processor into the compartment without any visual alignment of the first and second components of the connector.