Patents Assigned to Eidetic Communications Inc.
  • Patent number: 12222872
    Abstract: A method and apparatus for generating a histogram includes receiving an input key, determining if a linked-list node associated with the input key exists in the linked-list memory, in response to determining that a linked-list node associated with the input key does exist in the linked-list memory, increasing at least one count stored in the linked-list node associated with the input key, in response to determining that a linked-list node associated with the input key does not exist in the linked-list memory, determining if an available slot exists in the key storage memory, in response to determining that an available slot does not exist in the key storage memory determining a reclaimed slot in the key storage memory and a reclaimed node in the linked-list memory that is associated with the reclaimed slot, transmitting the data stored in the reclaimed slot in the key storage memory and the at least one count associated with the data stored in the reclaimed slot to an external device, and storing the key inpu
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: February 11, 2025
    Assignee: Eidetic Communications Inc.
    Inventors: Saeed Fouladi Fard, Stanley Jonathan Eskritt, Philip Chan, Sean Gregory Gibb
  • Patent number: 12222892
    Abstract: A system, and associated method, includes a plurality of data processing units, a target CPU, an interconnect unit that is separate from the target CPU and configured to receive a data payload and a prefix that includes a sequentially ordered list of the processing units that will perform the data operations and the sets of parameters to be used by each of the processing units, and based on the sequentially ordered list, the interconnect unit sends the data payload to a first processing unit, and receives back processed data, then sends the processed data to the subsequent processing unit, and receives back further processed data, and so forth until all of the data operations have been performed by the processing units set forth in the sequentially ordered list.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 11, 2025
    Assignee: Eidetic Communications Inc.
    Inventors: Sean Gregory Gibb, Saeed Fouladi Fard
  • Patent number: 12105811
    Abstract: A system and method that utilize an encryption engine endpoint to encrypt data in a data storage system are disclosed. In the system and method, the client controls the encryption keys utilized to encrypt and decrypt data such that the encryption keys are not stored together with the encrypted data. Therefore, once data is encrypted, neither the host of the data storage system, nor the encryption engine endpoint have access to the encryption keys required to decrypt the data, which increases the security of the encrypted data in the event of, for example, the data storage system being accessed by an unauthorized party.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: October 1, 2024
    Assignee: Eidetic Communications Inc.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Patent number: 11804852
    Abstract: Systems and methods are provided for mitigating effects of hash collisions in hardware data compression, for example reducing or avoiding the side effects of hash collisions, or reducing or avoiding slow downs caused by hash collisions. In an aspect, a processor-implemented method includes: hashing an input data byte sequence to produce a hash value, the input data byte sequence being located at a sequence address within an input data stream; and storing, in a hash table at a hash address corresponding to the hash value, the sequence address and a portion of the input data byte sequence. In an aspect, to further avoid hash collisions, hash memory accesses are distributed among a plurality of parallel hash banks to increase the throughput. Another aspect virtually extends a hash depth by extending a data match search around broken hash links, going backward in the data sequence.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 31, 2023
    Assignee: Eidetic Communications Inc.
    Inventors: Saeed Fouladi Fard, Sean Gibb
  • Patent number: 11687365
    Abstract: A computational storage processor (CSP) is provided that includes the CSP comprising a plurality of submission queues (SQs), a plurality of computational storage functions (CSFs), a CSF controller, and a CSP controller, and a method of controlling the CSP is provided that includes directing a first submission queue entry (SQE) that is written to a first one of the plurality of SQs to the CSF controller, generating, by the CSF controller, one or more secondary SQEs based on the first SQE, each of the one or more secondary SQEs is directed to a respective one of the CSFs, writing, by the CSF controller, the one or more secondary SQEs to a second one of the plurality of SQs, directing each of the one or more secondary SQEs to an associated respective one of the CSFs, and for each of the one or more secondary SQEs, performing, by the associated respective one of the CSFs, an operation associated with the secondary SQE.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: June 27, 2023
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Sean Gregory Gibb, Saeed Fouladi Fard
  • Patent number: 11468177
    Abstract: A system and method that utilize an encryption engine endpoint to encrypt data in a data storage system are disclosed. In the system and method, the client controls the encryption keys utilized to encrypt and decrypt data such that the encryption keys are not stored together with the encrypted data. Therefore, once data is encrypted, neither the host of the data storage system, nor the encryption engine endpoint have access to the encryption keys required to decrypt the data, which increases the security of the encrypted data in the event of, for example, the data storage system being accessed by an unauthorized party.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 11, 2022
    Assignee: Eidetic Communications Inc.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Patent number: 11372714
    Abstract: A method and a hardware accelerator device are provided for performing erasure coding on the hardware accelerator device that includes a dedicated buffer memory that is resident on the hardware accelerator device and that is connected to a second device via a bus, the method includes receiving, at the dedicated buffer memory, write data directly from the second device via the bus such that receiving the data at the dedicated buffer memory bypasses a buffer memory connected to a central processing unit (CPU), performing, at the hardware accelerator, an erasure coding operation on the write data received at the dedicated buffer memory to generate parity data based on the received write data, transmitting the parity data directly to a storage device connected to the hardware accelerator device via the bus such that transmitting the parity data bypasses the buffer memory connected to the CPU.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 28, 2022
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Patent number: 11231868
    Abstract: A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a central processing unit (CPU) via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: January 25, 2022
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Patent number: 10996892
    Abstract: Systems and methods are provided that facilitate performing hardware acceleration processes without utilizing specialized drivers that are software and hardware specific by controlling the hardware accelerator with NVMe commands. The NVMe commands may be based on standardized NVMe commands provided in the NVMe specification, or may be vendor-specific commands that are supported by the NVMe specification. The commands are sent to the NVMe accelerator by a host CPU which, in some embodiments, may be located remotely to the NVMe accelerator. The NVMe accelerator may include a CMB on which a host CPU may set up an NVMe queue in order to reduce PCIe traffic on a PCIe bus connecting the CPU and the NVMe accelerator. The CMB may also be used by a host CPU to transfer data for acceleration to reduce bandwidth in the DMA controller or to remove host staging buffers and memory copies.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: May 4, 2021
    Assignee: Eidetic Communications Inc.
    Inventors: Sean Gibb, Roger Bertschmann
  • Publication number: 20200210597
    Abstract: A system and method that utilize an encryption engine endpoint to encrypt data in a data storage system are disclosed. In the system and method, the client controls the encryption keys utilized to encrypt and decrypt data such that the encryption keys are not stored together with the encrypted data. Therefore, once data is encrypted, neither the host of the data storage system, nor the encryption engine endpoint have access to the encryption keys required to decrypt the data, which increases the security of the encrypted data in the event of, for example, the data storage system being accessed by an unauthorized party.
    Type: Application
    Filed: December 13, 2019
    Publication date: July 2, 2020
    Applicant: Eidetic Communications Inc.
    Inventors: Stephen BATES, Saeed FOULADI FARD