Patents Assigned to EIpida Memory, Inc.
  • Publication number: 20050040804
    Abstract: A plate voltage generation circuit comprises: first and second differential circuits (11a, 11b) supplied with a reference voltage (VREF) and an output voltage (VOUT), respectively; a push-pull output circuit (3), connected to the first and second differential circuits, for generating the output voltage; and first and second dead-band control circuits, connected to the first and second differential circuits, respectively, for changing the width of a dead band of the output voltage in accordance with a high level or a low level of dead-band control signals (Sa, Sb) externally supplied.
    Type: Application
    Filed: June 29, 2004
    Publication date: February 24, 2005
    Applicants: EIpida Memory, Inc., Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.
    Inventors: Takeshi Hashimoto, Hiromitsu Kojima