Abstract: A metric and English socket wrench is rotatable about an axis, and includes an inner peripheral surface. The inner peripheral surface has first engaging portions, and second engaging portions arranged alternately with the first engaging portions. Each of the first engaging portions has two first engaging surfaces interconnected to form a V-shape. A first apex is disposed between the two first engaging surfaces, and is spaced apart from the axis by a first distance. Each of the second engaging portions has two second engaging surfaces interconnected to form a V-shape. A second apex is disposed between the two second engaging surface, and is spaced apart from the axis by a second distance. Ratio of the first distance to the second distance is more than 0.94 and less than 1.06.

Abstract: A clutch includes a drive body disposed in a hollow base and having a plurality of force-bearing surfaces each cooperating with the hollow base to define an accommodating space therebetween. A clutching component is received in the accommodating space, and abuts against the hollow base and the force-bearing surface at first and second contact points, respectively. An angle between two lines, passing respectively through the first and second contact points and intersecting at a center of the clutching component, is greater than 160° and smaller than 180°. A ratio of a maximum distance between the inner annular surface and the force-bearing surface to a cross-sectional dimension of the clutching component is greater than 1 and smaller than 1.1.

Abstract: A video synchronization signal generating circuit includes a sample and hold circuit, a voltage divider and an amplifier. The voltage divider produces an adaptive voltage level based at least in part on an output of the sample and hold circuit. The amplifier, which receives a video signal, is connectable by switches in different configurations. In a first configuration the amplifier acts as a comparator to compare the adaptive voltage level with the video signal. An output of the amplifier in the first configuration is an output of the video synchronization signal generating circuit. In a second configuration the amplifier forms part of the sample and hold circuit.

Abstract: Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A laser driver serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register of the laser driver, and the data bits are serially shifted into a data shift register of the laser driver. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers of the laser driver. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Abstract: Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A laser driver serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register of the laser driver, and the data bits are serially shifted into a data shift register of the laser driver. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers of the laser driver. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Abstract: Methods and system are provided for automatic power control of a laser diode, e.g., in a laser driver. In accordance with an embodiment of the present invention, a power controller includes a detector circuit adapted to detect the output of the laser diode and to produce a measured output therefrom. A comparator compares a desired output to the measured output, and produces an error signal therefrom. The error signal is provided to an integrator circuit that produces an integrated error signal. At least one digital-to-analog converter (DAC) uses the integrated error signal to produce a current drive signal that drives the laser diode.

Abstract: Input stages for use in multiplexing, and methods for using the same, are provided herein. An input stage includes an input terminal and an output terminal. A voltage input signal is accepted at the input terminal of the input stage. When the input stage is selected, a substantially unmodified version of the voltage input signal is presented at the output terminal of the input stage, when the input stage is selected. When the input stage is deselected, a rejection voltage signal is produced, where the rejection voltage signal is of substantially equal magnitude and opposite polarity to the corresponding voltage input signal in order to reject the voltage input signal and thereby present a substantially constant voltage at the output terminal of the input stage regardless of variations in the voltage input signal.

Abstract: Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A laser driver serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register of the laser driver, and the data bits are serially shifted into a data shift register of the laser driver. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers of the laser driver. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Abstract: A video synchronization signal generating circuit includes a sample and hold circuit, a voltage divider and an amplifier. The voltage divider produces an adaptive voltage level based at least in part on an output of the sample and hold circuit. The amplifier, which receives a video signal, is connectable by switches in different configurations. In a first configuration the amplifier acts as a comparator to compare the adaptive voltage level with the video signal. An output of the amplifier in the first configuration is an output of the video synchronization signal generating circuit. In a second configuration the amplifier forms part of the sample and hold circuit.

Abstract: Input stages for use in multiplexing, and methods for using the same, are provided herein. An input stage includes an input terminal and an output terminal. A voltage input signal is accepted at the input terminal of the input stage. When the input stage is selected, a substantially unmodified version of the voltage input signal is presented at the output terminal of the input stage, when the input stage is selected. When the input stage is deselected, a rejection voltage signal is produced, where the rejection voltage signal is of substantially equal magnitude and opposite polarity to the corresponding voltage input signal in order to reject the voltage input signal and thereby present a substantially constant voltage at the output terminal of the input stage regardless of variations in the voltage input signal.

Abstract: Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A laser driver serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register of the laser driver, and the data bits are serially shifted into a data shift register of the laser driver. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers of the laser driver. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Abstract: A multiplexer circuit includes a plurality of switched differential amplifier circuits, one of which can be selected at a time. Each switched differential amplifier includes a pair of differential inputs and a pair of differential outputs, with each pair of differential inputs accepting a corresponding pair of input signals. Each of the switched differential amplifier circuits is configured to present a current mode version of its input signals at its differential outputs when the switched differential amplifier circuit is selected, and to present substantially zero level output signals at its differential outputs when the switched differential amplifier circuit is deselected. The multiplexer circuit also includes a selector that accepts a select signal and selects one of the plurality of switched differential amplifier circuits based on said select signal. A current mirror is used to combine a pair of multiplexer outputs into a single ended output, a version of which is used for feedback.

Abstract: Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register, and the data bits are serially shifted into a data shift register. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700,702,704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments.

Abstract: Differential amplifiers are provided that substantially cancel the input bias currents at the inputs to the differential amplifiers. A circuit produces a compensation current that is substantially equal in magnitude but opposite in polarity to input bias currents associated with the first and second inputs of the differential amplifier. A further pair of transistors are used to replicate the compensation current, and to provide replicated compensation currents to the inputs of the differential amplifier, thereby substantially canceling the input bias currents at the inputs.

Abstract: Methods and systems and apparatuses for reducing power consumption, in an environment including a laser driver that drives a laser diode, are provided. The voltage drop across a laser diode, driven by a laser driver, is monitored. This enables a supply voltage, used to power the laser driver, to be appropriately adjusted, based at least in part on the monitored voltage drop. For example, the supply voltage is increased when the monitored voltage drop across the laser diode increases, and decreased when the monitored voltage drop across the laser diode decreases.

Abstract: Methods and system are provided for automatic power control of a laser diode, e.g., in a laser driver. In accordance with an embodiment of the present invention, a power controller includes a detector circuit adapted to detect the output of the laser diode and to produce a measured output therefrom. A comparator compares a desired output to the measured output, and produces an error signal therefrom. The error signal is provided to an integrator circuit that produces an integrated error signal. At least one digital-to-analog converter (DAC) uses the integrated error signal to produce a current drive signal that drives the laser diode.

Abstract: Circuits and methods for coherent noise cancellation are provided. More specifically, circuits and methods are provided for coherent cancellation of noise that is present in a data signal due to noise being present in the source signal (e.g., an optical signal) that is used to produce the data signal. The circuits, which use a subtraction process rather than division, are easy to implement in a chip, and provide for wide bandwidth performance.

Abstract: Differential amplifiers are provided that substantially cancel the input bias currents at the inputs to the differential amplifiers. A circuit produces a compensation current that is substantially equal in magnitude but opposite in polarity to input bias currents associated with the first and second inputs of the differential amplifier. A further pair of transistors are used to replicate the compensation current, and to provide replicated compensation currents to the inputs of the differential amplifier, thereby substantially canceling the input bias currents at the inputs.