Abstract: A current feedback amplifier having circuitry in its input stage for matching the error current created due to a parasitic capacitance (C.sub.IN) on the negative, or inverting input terminal (V.sub.IN-). Additional circuitry in the input stage subtracts the matching current from the error current created by C.sub.IN to cancel the error current due to C.sub.IN and thus eliminate the peaking of gain at high frequencies caused by C.sub.IN. In addition to cancellation of C.sub.IN errors, the subtraction process in the input stage enables cancellation of error current resulting from bias current common mode rejection (ICMR) as well as component dissimilarities created during processing.

Abstract: A capacitance compensation circuit for a current feedback amplifier which compensates for error current created due to a parasitic capacitance C.sub.IN on the negative, or inverting input terminal V.sub.IN. The capacitance compensation circuit includes a capacitor C* connected to the positive input terminal V.sub.IN+ utilized to couple current from V.sub.IN+ to the collectors of emitter follower transistors having bases coupled to V.sub.IN+ and emitters connected to V.sub.IN-.

Abstract: A current feedback amplifier having circuitry in its input stage for matching the error current created due to a parasitic capacitance (C.sub.IN) on the negative, or inverting input terminal (V.sub.IN-). Additional circuitry in the input stage subtracts the matching current from the error current created by C.sub.IN to cancel the error current due to C.sub.IN and thus eliminate the peaking of gain at high frequencies caused by C.sub.IN. In addition to cancellation of C.sub.IN errors, the subtraction process in the input stage enables cancellation of error current resulting from bias current common mode rejection (ICMR) as well as component dissimilarities created during processing.

Abstract: A current feedback circuit for controlling the error current in current feedback amplifier includes transistor biasing circuitry which monitors the error current to detect high input signal slew rates and switches on a transistor controlled shunt circuit to divert drive current from the transistors forming the amplifier input, when the error current generated exceeds a threshold value.

Abstract: A current compensation circuit for a comparator includes a pair of switching transistors which supply input bias current to their corresponding comparator input transistors, a pair of current to voltage conversion means which use collector current from the comparator input transistors to turn on and off the appropriate switching transistor when its corresponding comparator input transistor is on, a transistor to generate a negative replica of the input bias current flowing in the comparator input, and a current mirror which is programmed by the replica of the uncompensated input bias current to produce a compensated input bias current to the switching transistors.

Abstract: A logic-controlled circuit superimposes a constant voltage across an actuator or motor load that is driven by a bridge-type amplifier to control the constant velocity operation of such load in response to an applied logic signal that may also disable the bridge-type amplifier.

Abstract: An improved direct-coupled transistor amplifier circuit includes a pair of complementary conductivity type output transistors that are quiescently biased to slightly conductive state to provide low distortion amplification and temperature stabilized operating conditions. A pair of complementary conductivity type input transistors receive bias current having a value that is substantially matched to the change with temperature of base-emitter voltage of an input transistor divided by the value of a resistor connecting the emitter of the input transistor to receive the bias current.

Abstract: A bridge-type linear amplifier includes separate local feedback networks on each half-side channel of the amplifier and an additional feedback network between channels of the amplifier in order to correct for differences in current gains of output transistors and requisite drive currents.

Abstract: An overload protection circuit for a disableable amplifier includes a sensing resistor connected to provide indication of the current supplied to the amplifier and includes logic circuitry for producing a disabling control signal for a selected time interval following detection of the overload condition of the amplifier.

Abstract: An improved linear amplifier circuit includes controlled current sources connected to supply additional current to the output stage during rapid change of applied signal. The current sources are responsive to current levels in the input stages and thus need only conduct low levels of current during quiescent operating conditions. Symmetrical and asymmetrical circuit configurations with respect to reference potential are disclosed.

Abstract: An improved linear amplifier circuit includes current mirror circuits that are cross connected in the collector circuits of input transistors for supplying proportional current to circuit nodes from which signal is derived for controlling the output stages. The states for supplying boost current to the circuit nodes are stabilized in quiescent condition to avoid delays commonly associated with the turning on of a non-conducting stage.

Abstract: An improved direct-coupled amplifier includes a push-pull pair of transistors in an output stage that provides high output current on low quiescent current. Each such output transistor is driven by a push-pull pair of driver transistors that receives the applied signal at proper bias levels provided by forward-biased diodes (or diodes and gain element) to provide high input impedance to low output impedance signal buffering with wide bandwidth at high power levels.

Abstract: An improved gain stage includes a pair of differentially-connected, matched, bipolar transistors and local positive feedback from the output to the collector electrode of one input transistor to provide D.C. balance and substantially enhanced voltage gain.