Abstract: An analog switch includes n-channel and p-channel MOSFETs formed in a surface of a semiconductor substrate. Each of the n-channel and p-channel MOSFETs has first, second and third diffused regions which are formed in the semiconductor surface with the width thereof substantially equal to each other. The first and third diffused regions are spaced from the second diffused region to form first and second channel regions, respectively. Each of the n-channel and p-channel MOSFETs has first and second gate electrodes which are interconnected in common to each other and placed on respective gate insulating layers overlaying the first and second channel regions, respectively. The first gate electrode has an end portion extending over part of the second diffused region by a predetermined length, while the second gate electrode has an end portion extending over another part, opposite to the earlier-mentioned part, of the second diffused region by a predetermined length.

Abstract: An LPC analyser calculates LPC coefficients using signals bandlimited to half the sampling frequency of the LPC coefficients to be calculated. Thef calculated LPC coefficients are continuous in time scale and free from aliasing distortion. A bandlimiting circuit suitable for use in the LPC analyser is also disclosed.

Abstract: A MOS current switching circuit comprises a first MOSFET, a second MOSFET, a first control circuit, a second control circuit, and an inverting amplifier. The inverting amplifier receives an output voltage of a current source to provide a feedback bias voltage to the first and second control circuit which are controlled by a control signal. The first and second control circuits are complementary operated to each other in response to the control signal to provide the feedback bias voltage to the gate electrode of the first or second MOSFET. The first or second MOSFET passes selectively a noiseless constant current from the current source toward the output terminal.

Abstract: In a printed circuit board having a glass substrate, signal line conductors having uniform resistances are formed of a thin film of ITO or SnO.sub.2 alone, while a power supply conductor whose voltage drop is small is formed of a film of ITO or SnO.sub.2, a film of Ni plating, a film of Au plating and a thick film of metal formed of plating or paste. Bonding pads are formed of a thin film of ITO or SnO.sub.2, a film of Ni plating and a film of Au plating.

Abstract: An instruction decoder, for a variable byte processor, is capable of making the variable byte processor operate at a high processing speed and high byte efficiency.

Abstract: An optical head assembly for use with an optical disk apparatus includes a magnetic circuit block having permanent magnets each being elongate in a track traversing direction and a yoke for forming a magnetic circuit which conducts a magnetic field generated by the permanent magnets. The yoke includes a first through hole extending in a focusing direction, magnetic gaps located at opposite sides of the first through hole in the track traversing direction and individually accommodating the permanent magnets, and a second through hole for admitting the light beam issuing in the track traversing direction to guide it to the first through hole. The first through hole and magnetic gaps each has a cross-section relatively long in the track traversing direction. A beam deflector is loosely fitted in the first through hole for deflecting in the focusing direction the light beam which is incident thereto from the second through hole. The beam deflector is supported by a carriage.

Abstract: A frame memory control system includes independent row address counters for generating first and second row addresses, and selectors for selecting one or the other of these addresses, enabling data to be transferred to the frame memory at one rate and read out of the frame memory at another rate. For interlaced scanning, field detection circuits detect even and odd fields and generate signals which can be substituted for the most significant bits of the row addresses under control of an interlaced-mode signal, so that even-field data can be stored in one half of the frame memory and odd-field data in the other. This frame memory control system utilizes the frame memory efficiently, and can be employed with both sequential-scanning and interlaced-scanning raster display devices.

Abstract: A page printer with an internal CPU, interrupt controller, and DMAC has a DMA stopping circuit in the DMAC, the function of which is to stop a DMA transfer in response to a DMA stop signal and restart it in response to a DMA restart signal. The DMA signal is generated by the interrupt controller when it receives certain interrupt requests, such as communication interrupt requests, enabling the CPU to service these requests promptly. The DMA restart signal is generated at the end of the interrupt service routine. This arrangement permits DMA transfers to be performed in burst mode, stopping only when urgent interrupt service is required. Burst-mode DMA improves the speed of operation of the printer.

Abstract: In a voltage detection circuit, a comparison voltage generator includes reference-setting capacitors, each having a first terminal connected to a comparison voltage node, and switching circuits provided in association with the respective reference-setting capacitors, each switching circuit selectively connecting a second terminal of the associated reference setting capacitor either to a first potential node or to a second potential node.

Abstract: A lead frame for semiconductor devices comprises a plurality of lead sets, each made of a metal strip of a plurality of leads arranged side by side with a small clearance therebetween and a connecting member for integrally connecting the leads. A plurality of such lead sets are arranged in desired positions with respect to each other to form a lead frame assembly.

Abstract: In an apparatus for processing embossed characters on an embossed card, a sensing head has sensing wires extending generally parallel with each other in a first direction, the tips of the sensing wires disposed at different positions along a second direction orthogonal to the first direction. The sensing wires are repeatedly actuated toward their tips. Advancement of each sensing wire exceeding a predetermined distance is detected and electrical signals indicating the results of detection are produced. The embossed card is moved relative to the sensing head in a third direction orthogonal to the first and second directions, with the surface of the embossed card held parallel with the second and third directions, and close to the tips of the sensing wires.

Abstract: In a wire dot print head having print wires extending through an opening of a guide nose, the guide nose comprises two halves. The print head may further comprise a wire guide which is fitted in the guide nose and through which the print wires extend, and the wire guide may be clamped by the two halves. In another embodiment, the half members have abutting surfaces provided with semi-circular grooves, which when the guide nose halves are assembled, form guide holes in which the print wires are slidably supported. The use of the two halves facilitates assembly of the print head and reduces noise.

Abstract: A magneto-optical recording medium includes one selected from a compound of strontium titanate (SrTiOx), a compound of barium titanate (BaTiOx), a nitrogen compound of strontium titanate (SrTiOxNy), and a nitrogen compound of barium titanate (BaTiOxNy). The magneto-optical recording medium has a large value for the refractive index n and a small value for the extinction coefficient k; moreover, the medium is resistive against corrosions. For the magneto-optical recording medium, there is produced a protective film by simultaneously sputtering a film forming target and a composition adjusting target. The deposition of the protective film is achieved in a mixed atmosphere of an inert gas and oxygen or in a mixed gas of an inert gas and nitrogen.

Abstract: A dynamic random access memory system comprising a memory cell matrix, a row address decoder connected to the memory matrix and a counter for producing internal address signals to refresh the cells of the memory cell matrix. A row address buffer converts the external address signals to row address signals in response to an address buffer enabling signal, and a switching circuit connected to the counter and the row address buffer is selectively switching between the counter and the row address buffer in response to an address switching signal. A decoder circuit connected to the output of the switching circuit decodes selected address signals and provides decoded address signals to the row address decoder.

Abstract: In a process of fabricating a MISFET of the LDD structure, a gate insulation film is formed on a semiconductor substrate or a semiconductor thin film. A gate electrode is formed on the gate insulation film, and lightly-doped regions are formed in the semiconductor substrate or the semiconductor thin film by ion implantation using the gate electrode as a mask. Next, a CVD oxide film containing an impurity is unselectively deposited, sidewalls are formed along the edges of the gate electrodes by anisotropic etching, and heavily-doped source and drain regions are formed in the semiconductor substrate or the semiconductor thin film by ion implanation using the gate electrode and the sidewalls as a mask.

Abstract: In a semiconductor integrated circuit fabrication method, isolated regions are in a silicon substrate, which is then covered with polysilicon, a passive base region is then formed, the polysilicon is selectively oxidized, the unoxidized polysilicon is then doped at first and second concentrations, a surface insulating layer is then deposited, the dopant is then diffused from the polysilicon to create further passive and active base regions, contact holes are then opened, the polysilicon above the active base is then doped, and this dopant is then diffused to create an emitter region in the active base. By employing a polysilicon layer with reduced initial thickness, this fabrication method enables precise doping with excellent control over the active base concentration, junction depth, polysilicon sheet resistance, and other parameters.

Abstract: In an apparatus for and a method of ion implantation for implanting boron (B) and/or arsenic (As) ions in a substrate surface, a four-element alloy of platinum, silicon, arsenic, and boron or a three-element alloy of copper (Cu), arsenic, and boron is held in a reservoir in a molten state. The alloy is then supplied from the reservoir to an emitter, and a strong electric field is applied to the tip of the emitter to extract ions from the tip of the emitter. The reservoir and emitter may be a refractory metal selected from W, Mo, and Ta, at least the surface of which has been nitrided.