Abstract: A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.
Type:
Grant
Filed:
June 29, 2016
Date of Patent:
August 21, 2018
Assignees:
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
Abstract: A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.
Type:
Grant
Filed:
December 7, 2016
Date of Patent:
February 27, 2018
Assignees:
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
Inventors:
Jinping Zhang, Zehong Li, Jingxiu Liu, Min Ren, Bo Zhang, Zhaoji Li
Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.
Type:
Grant
Filed:
July 13, 2016
Date of Patent:
August 22, 2017
Assignees:
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC
Inventors:
Jinping Zhang, Yadong Shan, Gaochao Xu, Xin Yao, Jingxiu Liu, Zehong Li, Min Ren, Bo Zhang