Patents Assigned to Electronic Packaging Co.
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Publication number: 20200381574Abstract: An optical sensing chip packaging structure includes a substrate, an optical sensing member, a light emitting member, a transparent glue layer and a transparent cover plate, wherein the optical sensing member is positioned on the substrate; the light emitting member is positioned on the optical sensing member, and the light emitting member includes a light emitting surface; the transparent glue layer is positioned on the light emitting member, and contacts and covers the light emitting surface; the transparent cover plate is positioned on the transparent glue layer.Type: ApplicationFiled: September 13, 2019Publication date: December 3, 2020Applicant: TAIWAN ELECTRONIC PACKAGING CO., LTD.Inventor: CHERNG-CHIAO WU
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Patent number: 10811399Abstract: An optical sensing chip packaging structure includes a substrate, an optical sensing member, a light emitting member and a transparent cover plate. The substrate has a recess; the optical sensing member is positioned in the recess, and is electrically connected to the substrate. The light emitting member is positioned in the recess, and is electrically connected to the substrate or the optical sensing member. The transparent cover plate is positioned on the substrate, and covers the optical sensing member and the light emitting member.Type: GrantFiled: March 27, 2019Date of Patent: October 20, 2020Assignee: TAIWAN ELECTRONIC PACKAGING CO., LTD.Inventor: Cherng-Chiao Wu
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Publication number: 20200312827Abstract: An optical sensing chip packaging structure includes a substrate, an optical sensing member, a light emitting member and a transparent cover plate. The substrate has a recess; the optical sensing member is positioned in the recess, and is electrically connected to the substrate. The light emitting member is positioned in the recess, and is electrically connected to the substrate or the optical sensing member. The transparent cover plate is positioned on the substrate, and covers the optical sensing member and the light emitting member.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: TAIWAN ELECTRONIC PACKAGING CO., LTD.Inventor: CHERNG-CHIAO WU
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Publication number: 20070272846Abstract: An image chip package structure includes a carrier member, an image sensing die, a protective shield and a plurality of wires. The image sensing die has a side connected to the carrier and an opposite side with an image sensing region and a plurality of die bonding pads around the image sensing region. The protective shield has a connecting portion and a top shield portion. The connecting portion is connected to the image sensing die between the image sensing region and the die bonding pads to isolate the image sensing region and the die bonding pads and to surround the image sensing region. The top shield portion is connected to the connecting portion and above the image sensing region. The wires electrically connect the die bonding pads of the image sensing die and the carrier member.Type: ApplicationFiled: August 8, 2007Publication date: November 29, 2007Applicant: Taiwan Electronic Packaging Co., Ltd.Inventor: Cheng-Chiao WU
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Patent number: 7210752Abstract: A telescoping slide rail assembly including interconnected mounting, intermediate and stationary slide rails movable relative to one another to extend and retract the mounting and intermediate slide rails relative to the stationary slide rail between fully extended and retracted positions. The intermediate slide rail includes a latching mechanism for interconnecting the intermediate and stationary slide rails in the fully extended position and the mounting slide rail includes an alignment device to maintain orientation between the mounting slide rail and the intermediate slide rail.Type: GrantFiled: August 24, 2006Date of Patent: May 1, 2007Assignee: Pentair Electronic Packaging Co.Inventor: William Dubon
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Publication number: 20060284531Abstract: A telescoping slide rail assembly including interconnected mounting, intermediate and stationary slide rails movable relative to one another to extend and retract the mounting and intermediate slide rails relative to the stationary slide rail between fully extended and retracted positions. The intermediate slide rail includes a latching mechanism for interconnecting the intermediate and stationary slide rails in the fully extended position and the mounting slide rail includes an alignment device to maintain orientation between the mounting slide rail and the intermediate slide rail.Type: ApplicationFiled: August 24, 2006Publication date: December 21, 2006Applicant: PENTAIR ELECTRONIC PACKAGING CO.Inventor: William Dubon
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Patent number: 6938967Abstract: A telescoping slide assembly includes interconnected mounting, intermediate and stationary slide elements movable relative to one another to extend and retract the mounting and intermediate slide elements relative to the stationary slide element between fully extended and retracted positions. The intermediate slide element includes a rib formed therein. A mounting slide lock is disposed substantially within the rib for operative engagement with the mounting slide element to secure the mounting slide element in a fully extended position such that selective release of the mounting slide lock permits the mounting slide element to move to the fully retracted position and to disconnect from the intermediate slide element.Type: GrantFiled: December 12, 2002Date of Patent: September 6, 2005Assignee: Pentair Electronic Packaging Co.Inventors: William Dubon, Ronan Stephens
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Patent number: 6635953Abstract: An IC chip package is constructed to comprise a substrate, a chip, adhesive means, and a cover. The substrate comprises a top side and a receiving chamber, the receiving chamber having an opening disposed in the top side. The top side of the substrate is provided with a plurality of connecting pads arranged around the opening of the receiving chamber. The chip is fixedly mounted in the receiving chamber and is provided with a plurality of connecting pads respectively electrically connected to the connecting pads of the substrate by means of bonding wires. The adhesive means is applied on the connecting area between the bonding wires and the connecting pads of the substrate. The cover is fixedly fastened to the adhesive means to close the opening of the receiving chamber.Type: GrantFiled: January 7, 2002Date of Patent: October 21, 2003Assignee: Taiwan Electronic Packaging Co., Ltd.Inventor: Cheng-Chiao Wu
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Publication number: 20020089039Abstract: An IC chip package is constructed to comprise a substrate, a chip, adhesive means, and a cover. The substrate comprises a top side and a receiving chamber, the receiving chamber having an opening disposed in the top side. The top side of the substrate is provided with a plurality of connecting pads arranged around the opening of the receiving chamber. The chip is fixedly mounted in the receiving chamber and is provided with a plurality of connecting pads respectively electrically connected to the connecting pads of the substrate by means of bonding wires. The adhesive means is applied on the connecting area between the bonding wires and the connecting pads of the substrate. The cover is fixedly fastened to the adhesive means to close the opening of the receiving chamber.Type: ApplicationFiled: January 7, 2002Publication date: July 11, 2002Applicant: TAIWAN ELECTRONIC PACKAGING CO., LTD.Inventor: Cheng-Chiao Wu
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Patent number: 5485081Abstract: A system for reducing the number of points to be tested on a printed circuit board where the printed circuit board includes a plurality of network traces each having end points and a plurality of pads provides for the identification of the end points of each network trace of the plurality of network traces. Certain ones of the plurality of network traces network located within a predetermined distance of one another are grouped to form a plurality of groups of network traces. The identified end points of the grouped network traces are connected together within each group of network traces to form a continuous trace having one pair of end points for each group of network traces. The end points are used for testing the printed circuit board.Type: GrantFiled: May 14, 1992Date of Patent: January 16, 1996Assignee: Electronic Packaging Co.Inventors: Robert E. Whitehead, Evan J. Evans, Stephen J. Foster
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Patent number: 5124633Abstract: A system for reducing the number of points to be tested on a dual sided printed circuit board. The circuit board includes a top and a bottom surface and a plurality of network traces extending across both sides of the printed circuit board. Each network trace includes end points. The system provides for identifying the end points of a network trace extending on both sides of the printed circuit board. The mid-point along the network trace which is common to both sides of the printed circuit board is identified. Structure is provided for independently testing each side of the printed circuit board between one end point and the mid-point on the top surface of the printed circuit board and between the mid-point and the second end point on the bottom surface of the printed circuit board.Type: GrantFiled: January 10, 1991Date of Patent: June 23, 1992Assignee: Electronic Packaging Co.Inventors: Robert E. Whitehead, Evan J. Evans, Stephen J. Foster
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Patent number: 4469553Abstract: A printed circuit board operation system includes a work station for receiving, orienting and retaining a printed circuit board to be operated upon. A product storage array is located adjacent the work station and comprises structure for storing and designating individual components to be assembled onto the printed circuit board in the work station. A visual image projection system is provided for generating a series of visual images each comprising an operational step to be performed on the printed circuit board. Each image is projected in a location and in an orientation corresponding to the correct positioning and orientation of the operation to be performed on the printed circuit board. Verbal instruction generating structure is also provided for producing a series of verbal instructions corresponding to the operational steps. The printed circuit board operation system may be utilized to direct the assembly, repair, modification or testing of printed circuit boards.Type: GrantFiled: June 27, 1983Date of Patent: September 4, 1984Assignee: Electronic Packaging Co.Inventor: Robert E. Whitehead
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Patent number: D554485Type: GrantFiled: December 13, 2005Date of Patent: November 6, 2007Assignee: Pentair Electronic Packaging Co.Inventor: William Dubon
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Patent number: D562117Type: GrantFiled: December 13, 2005Date of Patent: February 19, 2008Assignee: Pentair Electronic Packaging Co.Inventor: William Dubon
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Patent number: D392199Type: GrantFiled: December 27, 1996Date of Patent: March 17, 1998Assignee: Electronic Packaging Co.Inventors: Evan J. Evans, Raymond DeWine Heistand, II