Abstract: A memory device having unmultiplexed address inputs for performing an address control function including an address control input (AC) port, address inputs and an address arithmetic unit which performs the address control function by summing up these inputs. These units are connected such that the summed address of the address inputs and the address control input is applied to the memory as the actual address. Also provided is a memory device having multiplexed address inputs for performing an address control function including an address control input (AC) port, a row address select input (RAS) port, and an address arithmetic unit for performing an address control function by controlling these ports.