Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

Abstract: A video decoding method includes determining, based on an area of a current block, whether a multi-prediction combination mode for predicting the current block by combining prediction results obtained according to a plurality of prediction modes is applied to the current block, when the multi-prediction combination mode is applied to the current block, determining the plurality of prediction modes to be applied to the current block, generating a plurality of prediction blocks of the current block, according to the plurality of prediction modes, and determining a combined prediction block of the current block, by combining the plurality of prediction blocks according to respective weights.

Abstract: An image sensor comprises a first and second chips. The first chip includes a first semiconductor substrate, a photoelectric conversion layer in the first semiconductor substrate, a color filter, a micro lens, a first transistor adjacent to the photoelectric conversion layer, a first insulating layer, and a first metal layer in the first insulating layer and connected to the first transistor. The second chip includes a second insulating layer, a second semiconductor substrate, a second transistor on the second semiconductor substrate, a second metal layer in the second insulating layer and connected to a gate structure of the second transistor through a gate contact, a landing metal layer below the second metal layer, and a through via in direct contact with the landing metal layer and vertically passing through the second semiconductor substrate. A width of the through via becomes narrower as the width approaches the third surface.

Abstract: A meta-lens, an imaging optics, and an electronic device including the imaging optics are provided. The meta-lens includes at least one meta-layer having a plurality of nanostructures with a less shape dimension than an operating wavelength, modulates a phase and intensity of incident light, and forms a plurality of spots of different brightness on an imaging plane in an asymmetric distribution. The plurality of spots formed on the imaging plane include a main spot and at least one sub-spot that is separated from a center of the main spot and has lower illuminance than the main spot.

Abstract: A method of operating a non-volatile memory device is provided. The device includes a latch, a page buffer and blocks, each of which includes pages. The method includes: receiving a page command for a write operation corresponding to a page of one of the blocks; receiving a write command for writing data to the page buffer; latching preexisting latched data or random data generated as latched data; writing the latched data to a page of a new block from among the plurality of blocks that corresponds to a page address based on the write command; and repeatedly updating the page address and repeatedly writing the latched data to additional pages corresponding to each updated page address until each page of the new block has been written to.

Abstract: A cooking apparatus has a cooking chamber, a microwave unit to radiate microwaves to the cooking chamber, a convection unit to supply hot air to the cooking chamber, a grill unit to supply radiant heat to the cooking chamber, an input unit to receive a cooking command and a control unit to perform a cooking corresponding to the received cooking command by performing one of a first heating stage and a second heating stage, and after performing the one of the first heating stage and the second heating stage, performing the other one of the first heating stage and the second heating stage. In the first heating stage, the control unit operates the microwave unit and at least one of the convection unit and the grill unit, and in the second heating stage, the control unit operates the grill unit and the convection unit while not operating the microwave unit.

Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory, an interconnect, a device controller and a buffer memory. The interconnect exchanges data with a host, receives a logging target setting request and a logging period setting request with respect to debugging information from the host, receives a debugging information logging request from the host, and receive a read request from the host. The device controller includes a buffer memory and controls the non-volatile memory, controls a logging operation on the debugging information based on a logging target and a logging period, which are requested by the host, in response to the debugging information logging request, and transmits the debugging information to the host in response to the read request. The device controller is further configured to logs the debugging information in the buffer memory according to the debugging information logging request.

Abstract: Provided is a video decoding method of applying a deblocking filter to neighboring pixels adjacent to a boundary of a current block, the video decoding method including selecting a deblocking filter to be applied to the neighboring pixels from among a plurality of deblocking filters according to pixel values of the neighboring pixels and a size of the current block, and applying the selected deblocking filter to the neighboring pixels, wherein the plurality of deblocking filters include three or more deblocking filters having different ranges of neighboring pixels to which deblocking filtering is applied.

Abstract: Some example embodiments relate to a super resolution scanning electron microscope (SEM) image implementing device and/or a method thereof. Provided a super resolution scanning electron microscope (SEM) image implementing device comprising a processor configured to crop a low resolution SEM image to generate a first cropped image and a second cropped image, to upscale the first cropped image and the second cropped image to generate a first upscaled image and a second upscaled image, and to cancel noise from the first upscaled image and the second upscaled image to generate a first noise canceled image and a second noise canceled image.

Abstract: A color filter array may include a plurality of color filters arranged two-dimensionally and configured to allow light of different wavelengths to pass therethrough. Each of the plurality of color filters includes at least one Mie resonance particle and a transparent dielectric surrounding the at least one Mie resonance particle.

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Abstract: An image display device includes a processor that sets a location of a virtual image plane on which a virtual image is formed according to depth information included in first image data and generates second image data obtained by correcting the first image data based on the set location of the virtual image plane; an image forming optical system including a display element configured to modulate light to form a display image according to the second image data and a light transfer unit that forms the virtual image on the virtual image plane, the virtual image corresponding to the display image formed by the display element, the light transfer unit comprising a focusing member; and a drive unit that drives the image forming optical system to adjust the location of the virtual image plane.

Abstract: Provided is a meta optical device including a plurality of phase modulation regions respectively including a plurality of nanostructures and configured to modulate a phase of incident light, wherein a phase retardation profile of the plurality of phase modulation regions monotonically change with respect to light of a plurality of wavelength bands apart from each other, and wherein phase modulation ranges with respect to the light of the plurality of wavelength bands are different from each other.

Abstract: A semiconductor device and a method for fabricating the same is provided. The semiconductor device includes a lower semiconductor film, a buried insulating film, and an upper semiconductor film which are sequentially stacked; an element isolation film defining an active region inside the substrate and including a material having an etching selectivity with respect to silicon oxide; a first gate trench inside the upper semiconductor film; a first gate electrode filing a part of the first gate trench; a second gate trench inside the element isolation film; and a second gate electrode filling a part of the second gate trench, a bottom side of the element isolation film being inside the lower semiconductor film.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip.

Abstract: A dish washer includes a cabinet, a tub positioned inside the cabinet, a sump provided in a lower portion of the tub, a case brake provided on a side wall of the tub connected to the sump, and a filter device positioned below the tub inside the cabinet, to selectively filter or unfilter water received from a water supply source, and to supply the filtered water or the unfiltered water to the case brake, the water passed through the case brake is collected in the sump, the case brake is located higher than the sump to prevent a backflow of the water collected in the sump to the case brake.

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

Abstract: Provided is a video decoding method performed by a video decoding apparatus, the video decoding method including: determining prediction mode information of a current block and an index indicating a prediction candidate, from a bitstream; determining a prediction candidate list according to the prediction mode information; when the prediction mode information of the current block indicates a pre-set prediction mode, determining a motion vector indicated by the index indicating the prediction candidate from the prediction candidate list, and determining a prediction motion vector of the current block based on at least one of pieces of motion prediction information related to the motion vector; and determining a motion vector of the current block based on the prediction motion vector, wherein the pre-set prediction mode is a prediction mode different from a skip mode and a merge mode.

Abstract: According to an example embodiment, a video decoding apparatus may be provided. The video decoding apparatus may include a central processing unit (CPU) configured to parse first header data included in an input bit-stream and generate a first register set based on the parsed first header data; and a decoder configured to decode the input bit-stream based on input parameters obtained through the first register set, wherein CPU is configured to parse second header data included in a second bit-stream of the input bit-stream of a second frame subsequent to the first frame while the decoder decodes a first bit-stream corresponding to the first frame.

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure may include a dielectric layer including a trench; a conductive line in the trench; and a first cap layer on an upper surface of the conductive line. The first cap layer may include a graphene-metal composite including graphene and a metal mixed with each other.