Patents Assigned to ELECTRONICS CORPORATION
  • Publication number: 20100239212
    Abstract: An optical module includes a receptacle for receiving an optical connector attached to a distal end of an optical fiber, and a lens body having a contact surface coming into contact with the distal end of the optical fiber when the receptacle receives the optical connector. The lens body has the contact surface and an opposing surface opposing the contact surface, and further has a columnar base held by the receptacle, a lens portion formed on the opposing surface integrally with the base, and a flat portion. The lens portion is surrounded by the flat portion and is off-centered with respect to the base.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 23, 2010
    Applicants: NEC ELECTRONICS CORPORATION, TOKAI RUBBER INDUSTRIES, LTD.
    Inventors: KAZUHIRO MITAMURA, SHIGERU MORIBAYASHI, JUNICHI SHIMIZU, HIDEYUKI YAMADA, SHUNSUKE OKAMOTO, MASAHIKO TAKEDA, SHIGEKI ASAHI, HIROKI ITAKURA
  • Publication number: 20100241927
    Abstract: A data processing apparatus includes a non-volatile semiconductor memory configured to store a storage data and an additional data control circuit configured to generate an additional data and add the additional data to a main storage data, and the additional data is different between a first mode and a second mode. The additional data control circuit includes a first mode circuit configured to generate the additional data in the first mode; and a second mode circuit configured to generate the additional data in the second mode. The storage data contains a target data or an inversion data of the target data, as the main storage data and the additional data.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 23, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoshitaka Soma
  • Publication number: 20100238744
    Abstract: A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.
    Type: Application
    Filed: February 4, 2010
    Publication date: September 23, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Nobumitsu Yano
  • Publication number: 20100236531
    Abstract: In an engine 1 equipped with a supercharger 40 consisting of a compressor 41 having a plurality of blades 45 on a turbine shaft 42 and a turbine 42, at least one index means 44 is provided on the turbine shaft 42 or the plurality of blades 45, and a turbo angular velocity sensor 62, which detects a rotation of the index means 44 and a rotation of the plurality of blades 45 respectively, is provided and connected to an ECU 60. In the engine 1, also, a turbo angular velocity computing means, which calculates an angular velocity by obtaining a plurality of pulses per one rotation of the turbine shaft, is provided.
    Type: Application
    Filed: April 19, 2007
    Publication date: September 23, 2010
    Applicants: Yanmar Co., Ltd., Applied Electronics Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Kouji Shimizu, Takashi Miyamoto, Takao Kawabe, Tetsuo Sakaki, Isamu Kawashima, Toshiro Itatsu
  • Publication number: 20100240246
    Abstract: A connector assembly includes a housing, a light source located within the housing, and a cover element covering at least a portion of a mating face of the housing. The housing includes a connector that is arranged to electrically mate with a peripheral connector proximate to the mating face of the housing. The light source generates light directed toward the mating face of the housing to indicate a status of the connector. The cover element includes a light transmissive area that is positioned to receive the light generated by the light source and transmit the light outward from the mating face in order to indicate the status of the connector.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 23, 2010
    Applicant: Tyco Electronics Corporation
    Inventors: BRIAN JAMES WILLIAMS, WILLIAM EDWARD TANIS, III
  • Publication number: 20100238450
    Abstract: A fiber optic gyroscope using a low-polarization and polarization-maintaining hybrid light path comprises an optical meter head and a circuit signal processing part, The optical meter head comprises: a light source, a multi-functional integrated optic chip, a detector, a coupler and a fiber coil, wherein the light source is a low polarization light source and single mode fiber pigtail coupling; the input terminal of multi-functional integrated optic chip uses a single mode fiber, and the output terminal of multi-functional integrated optic chip adopts a polarization-maintaining fiber; the input fiber pigtail of the said detector is a single mode fiber; the coupler is a 2×2 polarization independence single mode fiber coupler; the fiber coil is a polarization-maintaining fiber. By adopting the scheme of the low-polarization and polarization-maintaining hybrid light path and the signal processing methods such as all-digital closed loop control and random overmodulation etc.
    Type: Application
    Filed: May 21, 2007
    Publication date: September 23, 2010
    Applicant: CHINA AEROSPACE TIMES ELECTRONICS CORPORATION
    Inventors: Wei WANG, Qingsheng YANG, Zhixin ZHANG, Yuxin XU, Weiliang QIN
  • Publication number: 20100241426
    Abstract: Techniques pertaining to noise reduction are disclosed. According to one aspect of the present invention, noise in an audio signal is effectively reduced and a high quality of a target voice is recovered at the same time. In one embodiment, an array of microphones is used to sample the audio signal embedded with noise. The samples are processed according to a beamforming technique to get a signal with an enhanced target voice. A target voice is located in the audio signal sampled by the microphone array. A credibility of the target voice is determined when the target voice is located. The voice presence probability is weighted by the credibility. The signal with the enhanced target voice is enhanced according to the weighed voice presence probability.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 23, 2010
    Applicants: Vimicro Electronics Corporation, Vimicro Corporation
    Inventors: Chen ZHANG, Yuhong Feng
  • Publication number: 20100241374
    Abstract: There are provided a signal detection process that derives coordinates in a device coordinate system in analysis data for abnormal signal data included in the analysis data of a semiconductor integrated circuit obtained from a semiconductor inspection apparatus; a coordinate conversion process that derives a correspondence between a coordinate in the device coordinate system and a coordinate in a design coordinate system in the design data of the semiconductor integrated circuit for a plurality of reference points in the semiconductor integrated circuit, and that derives a coordinate conversion formula between the device coordinate system and the design coordinate system; an error calculation process that derives a position error between a coordinate in the device coordinate system converted by the coordinate conversion formula and a coordinate in the design coordinate system; and a circuit extraction process that extracts a circuit related to the abnormal signal in the design data based on the coordinates of
    Type: Application
    Filed: February 16, 2010
    Publication date: September 23, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masafumi Nikaido
  • Patent number: 7800187
    Abstract: In a semiconductor device including a gate electrode buried in a trench of the device, the trench is constructed by a first opening with a uniform width the same as that of an upper portion of the first opening and a second opening beneath the first opening with a width larger than the uniform width. A bottom of a base region adjacent to the trench is adjacent to the second opening.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naoki Matsuura
  • Patent number: 7800918
    Abstract: There is provided a memory module that facilitates meeting the needs of high-speed performance and large capacity. It comprises first module substrates (101 through 108), each with multiple DRAM devices (11), and a second module substrate whereon the first modules (101 through 108) are mounted, signal line groups connected to the multiple first modules respectively are provided in parallel, and a controller LSI (50), connected to the multiple first modules respectively via the signal line groups provided in parallel, that converts the signal lines into fewer signal lines than the total number of the signal line groups and outputs the result is provided, and the second module substrate (20) is mounted on a motherboard (40).
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takanori Saeki
  • Patent number: 7800153
    Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: September 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Masahiko Hiratani
  • Patent number: 7801709
    Abstract: A simulation system includes an input acceptance unit that accepts a measured dimension of a transfer pattern; a calculation unit including a light intensity calculation unit that calculates a light intensity at each position, and a modified light intensity calculation unit that adds a modified value including the product of the light intensity and a tentative optical reaction coefficient to the light intensity, thereby giving a modified light intensity; and a decision unit that decides the threshold value and optical reaction coefficient by regression calculation such that a difference between the measured dimension and the calculated dimension becomes minimal under the modified light intensity, with a constant being the threshold value of the light intensity at a pair of edges defining the calculated dimension of the transfer pattern in the simulation.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yukiya Kawakami
  • Patent number: 7800233
    Abstract: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masaya Kawano, Koji Soejima, Yoichiro Kurita
  • Patent number: 7800668
    Abstract: In a conventional solid state imaging device, there is a room for improvement in sensitivity. In order to solve the problem, a solid state imaging device includes a semiconductor substrate and a light receiving portion. The light receiving portion is provided adjacent to a surface layer on the surface (a first surface) side of the semiconductor substrate. The surface of the light receiving portion is silicided. The solid state imaging device is one in which light from an object to be imaged incident on the back side (a second surface) of the semiconductor substrate is photoelectric-converted inside the semiconductor substrate, the light receiving portion receives electric charge generated by the photoelectric conversion, and the above mentioned object to be imaged is imaged.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Patent number: 7802039
    Abstract: An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and the memory controller controls a memory access based on the waiting time counted by the counter.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Morita
  • Patent number: 7800108
    Abstract: The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hidetaka Nambu
  • Patent number: 7800572
    Abstract: A liquid crystal display apparatus is composed of an LCD panel including data lines, and an LCD driver. The LCD driver includes: a positive drive circuit providing a positive data signal having positive polarity with respect to a ground level of the LCD driver for one of the data lines; and a negative drive circuit providing a negative data signal having negative polarity with respect to the ground level of the LCD driver for another one of the data lines.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masayuki Kumeta, Kouji Matsuura
  • Patent number: 7799693
    Abstract: Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second insulating film with a porous structure on the first insulating film; (d) forming a third insulating film different from the second insulating film on the second insulating film; (e) forming a via hole in the second and third insulating film by dry etching of the third insulating films; (f) removing a part of the first insulating film such that the surface of the first conductive layer is exposed at the bottom of the via hole and (g) forming a second conductive material film layer so as to fill the via hole.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Eiichi Soda
  • Patent number: 7800841
    Abstract: An optical object distance simulation device for reducing total optical path includes: a lens, an achromatic lens set, a first image lens, and a second image lens. The achromatic lens set disposes beside one side of the lens, the first image lens disposes beside one side of the achromatic lens set, and the second image lens disposes beside one side of the first image lens. The achromatic lens set is composed of a first lens and a second lens. The first lens is a double-concave lens. The second lens is a double-convex lens. One concave face of the double-concave tightly contacts with one convex face of the double-convex lens. Therefore, the lens, the achromatic lens set, the first image lens, and the second image lens match with each other in order to simulate real object distance for reducing an object distance between a test camera lens and a corresponding chart.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: September 21, 2010
    Assignee: Youngtek Electronics Corporation
    Inventors: Bily Wang, Kuei-Pao Chen, Chih-Ming Wang, Jui-Wen Pan
  • Patent number: 7800601
    Abstract: Disclosed is a display controlling apparatus including latch circuits for holding color data of a current line and a previous line, a latch circuit for holding a polarity signal of the previous line, and a recovery control circuit. The recovery control circuit controls a recovery switch from color data of the previous and current lines, a polarity signal and a recovery clock. For both driving method employing frame-based common inverting and the driving method employing line-based common inverting, the display/controlling apparatus recovers electric charge efficiently to provide for low power dissipation.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Makoto Miura