Abstract: A pluggable male terminator for use with a female ribbon cable connector. The terminator is comprised of three basic parts that can snap together. The three members are a shroud having openings in the top, a PC board with pins extending from opposed surfaces, and a cover with recesses therein. The pins are complementary in shape and size to the openings in the shroud and the recesses in the cover. Further, the pins are aligned with the openings in the shroud and the recesses. For assembly, the pins on the PC board are inserted into the recesses in the cover openings in the shroud and the parts are pushed together. The pins extending from the shroud are adapted to be inserted into recesses in the female ribbon cable connector.

Abstract: A bias source (R7,R8,C24) connected to a summing amplifier (Q1) produces a first DC bias at the amplifier input (emitter) and a second DC bias at the amplifier output (collector). A first circuit node (B) is AC coupled (22) to a luminance signal source (Y1, 18), DC coupled via a first resistor (R4) to the input of the summing amplifier and DC coupled via a first amplifier (28) to a luminance load (Y3,30). A second circuit node (A) is AC coupled (20) to a chrominance signal source (C1,18), DC coupled via a second resistor (R3) to the input (emitter, Q1) of the summing amplifier and DC coupled via a second amplifier (26) to a chrominance signal load (C3,30). A third amplifier (Q2) provides DC coupling of the output of the summing amplifier (Q1) to a composite video signal load (E,40).

Abstract: A VCR includes circuitry for controlling a cable converter unit, circuitry for detecting the presence of a television signal, and control code transmission circuitry for remotely controlling a cable converter unit. Advantageously, because the VCR is coupled to the output of the cable converter unit, the VCR can monitor the television signals received from the cable converter unit to ensure that commands sent to the cable converter unit from the VCR are executed. It is herein recognized that a skip list programmed into a VCR may be used by the VCR to control a cable box. That is, in response to a channel up command received by the VCR, the VCR would not change channels itself, but rather controls the cable box to select the next preferred channel entered in the skip list of the VCR. In this mode of operation, the channel tuning keys (e.g., CHAN UP, CHAN DN) of the VCR remote control are used to control an external source of signals, while the VCR mechanism control keys (e.g.

Abstract: A method and apparatus provide an equalization time delay to synchronize a plurality of paging transmitters in a simulcast paging system. A delay equalization circuit (41 ) appropriate for use with an analog input signal includes a coder/decoder (CODEC) (50) and a digital signal processor (DSP) (58). An analog input signal is digitized or sampled by an analog-to-digital converter (ADC) in the CODEC, producing corresponding digital values that are input to the DSP. The DSP employs a selected finite impulse filter to interpolate between the sampled digital values from the CODEC to provide enhanced resolution in delaying a signal output that is output. The DSP determines a major sample index and an interpolated filter index to achieve the desired equalization time delay. These variables define two delay intervals that are combined to provide the required equalization time delay.

Abstract: A fiber optic and electrical hybrid connector is disclosed for providing remote system connectivity management and verification, comprising a first fiber optic connector including a housing. A first electrical connector mounted to the housing of the first fiber optic connector is provided for data identification transmission. The first fiber optic connector is mated to a second fiber optic connector and the first electrical connector simultaneously mating to a second electrical connector. The first electrical connector includes a transistor having a 64 bit ROM, a 48 bit Serial Number, an 8 bit CRC and an 8 bit family code. The second electrical connector includes data lines connected to a PCB having visual signal illumination connectivity means and remote connectivity management means. The first elecrtrical connector derives power from the data signal lines of the second electrical connector.

Abstract: Methods are provided for generating a square wave of variable duty cycle using a microprocessor and an interval timer. The duty cycle can be changed without changing the period. The duty cycle is changed on a rising or a falling edge of the signal as desired.

Abstract: A audio mixer is disclosed in which selection of audio monitor signals is accomplished by an edit select switch and a plurality of monitor select switches on a monitor select portion of the mixer display. When the edit select switch is enabled, selection of audio monitor source signals is controlled by an editor. When the edit select switch is not enabled, audio monitor signals may be selected by the plurality of monitor select switches. Selection of audio monitor signals is achieved regardless of whether or not the mixer is under general crossfade control by an editor.

Abstract: A system which enables removal of phosphor from a CRT front panel flange. The system includes an air operated valve connected between a water supply and a nozzle. The air operated valve may be incrementally opened and closed, which enables a continuous stream of water to be discharged from the nozzle onto the phosphor to remove the phosphor. In addition, the system includes an air supply and a pair of speed controllers which control the rate at which the air operated valve opens and closes.

Abstract: Apparatus for generating video signals representing photographic images previously recorded in a frame on a photographic film-type medium includes an image pickup device which produces video signals in response to a light image of the projected photographic image, a digitizer which digitizes the produced video signals, a memory which stores a video frame interval of the digitized video signals, an enhancer which enhances digitized video signals read from the memory, and a digital signal processor which controls the image pickup device, the memory and the enhancer.

Abstract: A vehicle security system having a secure valet/programming switch. To either enter the system valet mode, or select a function via the valet/programming switch, the user must first enter a valid personal access code via the switch. To prevent an intruder from deciphering the personal code by trying various codes, the system ignores, after a preset number of successive invalid entries, further switch inputs for a preset period of time. When attempts to decipher the code are detected, the alarm is tripped, and the siren will sound. To accommodate various drivers of the same vehicle, more than one valid code can be stored in the system. Any of the personal access codes may be changed any time, but after the user's present code is entered.

Abstract: An operator input subsystem and an image signal processing subsystem are provided to a digital image processing system. The operator input subsystem comprises a CPU, a display device and an input device, whereas the image signal processing subsystem comprises a digital signal processor having a number of digitized signal correctors. For cases where the output results are expressible as smoothly differentiable continuous functions of the digitized input signal values and the processing parameters, the CPU receives the specified output results from the input device and the digitized input signal values and the current processing parameters from the digitized signal correctors. In response, the CPU determines the most optimal processing parameters for the digitized signal correctors to achieve the specified output results. The CPU provides the determined optimal processing parameters to the digitized signal correctors, which in turn use the parameters to correct the digitized signals.

Abstract: A video display for a television apparatus has a wide format display ratio and is synchronized with a first video signal representative of first picture. A PIP processor is responsive to a second video signal representative of a second picture to define an auxiliary picture smaller in size than the video display. A FIFO line memory stores successive lines of video information representative of the auxiliary picture, which are combined with certain successive lines of video information representative of the first picture. A counter initialized at a time corresponding to the start of each horizontal line of the first video signal generates a variable time delay. A FIFO control circuit successively initiates a transfer of the lines of video information representative of the auxiliary picture from the line memory for combination with the video information representative of the main picture after the variable time delay.

Abstract: A compressed audio/video, A/V, receiver provides A/V component timing reference signals (PTS's) coincident with reproduction of associated decompressed component signals. Synchronization apparatus generates a function of the difference of occurring component audio and video PTS's. This function, which is indicative of relative audio and video synchronization, is compared with a predetermined threshold value, and a mute control signal is generated when the threshold is exceeded. Muting circuitry, responsive to the control signal disables audio reproduction when the reproduced audio and video component signal timing deviate from mutual synchronization.