Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit generally includes an array of software-configurable general purpose processors, a globally shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors generally has access to the globally shared memory to execute one or more portions of a decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a schedule describing which of the one or more portions of the decoding program are to be executed by each of the software-configurable general purpose processors.

Abstract: An apparatus includes a processor, a graphics processing unit and a memory. The memory stores computer executable instructions. The computer executable instructions include a motion estimation kernel which when executed by the graphics processing unit performs motion estimation on a current frame using a reference frame. The current frame and the reference frame are stored in a globally shared memory of the graphics processing unit.

Abstract: An apparatus includes a processor, a graphics processing unit and a memory. The memory stores computer executable instructions. The computer executable instructions include a motion estimation kernel which when executed by the graphics processing unit performs motion estimation on a current frame using a reference frame. The current frame and the reference frame are stored in a globally shared memory of the graphics processing unit.

Abstract: An apparatus including a first module and a second module. The first module may be configured to receive video and audio content and process the video and audio content for distribution with video and audio encoding to various media platforms based upon a plurality of predefined settings. The second module may be configured to generate a single-page user interface through which a user may set the predefined settings.

Abstract: A system for managing delivery of video content. The system includes a controller and one or more players. The controller may be configured to control generation of a plurality of streams containing the video content based upon feedback regarding decoding at least one of the plurality of streams. The one or more players may be configured to select a stream from the plurality of streams, generate decoding statistics for the selected stream, and send the decoding statistics to the controller as the feedback.

Abstract: A system includes a stream controller. The stream controller may be configured to generate a plurality of output streams in response to the plurality of input streams. The stream controller may be further configured to (i) determine when one of the plurality of input streams becomes invalid, (ii) switch generation of an output stream associated with the invalid input stream from the invalid input stream to a valid one of the plurality of input streams, and (iii) when the invalid input stream becomes valid again, switch the generation of the output stream back to the now valid input stream.

Abstract: A method for upgrading software having steps (A) to (D) is disclosed. Step (A) may deny a first server access to read from and write to a database controlled by a second server while second software in the second server is being upgraded. The second software as upgraded may be incompatible with first software running in the first server. Step (B) may generate data in the first server in response to a current operation of the first software while the second software is being upgraded. Step (C) may update the database by transferring the data from the first server to the database through the second server after the upgrade of the second software has finished. The first server generally remains denied to read from the database. Step (D) may upgrade the first software to be compatible with the second software in response to finishing the current operation.

Abstract: An apparatus including a graphics processing unit, a processor and a memory. The memory stores computer executable instructions. The computer executable instructions, when executed by the processor, configure the graphics processing unit to store a current frame, at least one reference frame, and a reconstructed frame in a globally shared memory of the graphics processing unit.

Abstract: A system including one or more stream sources and a stream controller. The one or more stream sources may be configured to generate a plurality of input streams containing a given content at a plurality of bitrates, a plurality of resolutions, or a plurality of bitrates and resolutions. The stream controller may be configured to generate a plurality of output streams in response to the plurality of input streams. The stream controller may be further configured to (i) determine when one of the plurality of input streams becomes invalid, (ii) switch generation of an output stream associated with the invalid input stream from the invalid input stream to a valid one of the plurality of input streams, and (iii) when the invalid input stream becomes valid again, switch the generation of the output stream back to the now valid input stream.

Abstract: An apparatus comprising a graphics processing unit, a processor and a memory. The memory stores computer executable instructions. The computer executable instructions use (i) the graphics processing unit to perform prediction, decimation, transformation and quantization, and inverse-quantization and inverse-transformation and (ii) the processor to perform entropy encoding and rate control.

Abstract: Techniques are disclosed for employing a set of stream processors to greatly accelerate common video encoding and transcoding tasks, with the goal of making these tasks run at a reasonable rate on off-the-shelf hardware. Stream processors are most commonly found in the graphics processing unit (GPU), a commodity piece of computer hardware used to generate images for display. Embodiments of the invention are particularly advantageous to accelerate video encoding and transcoding tasks in which the blocks being processed have dependencies on their neighboring blocks.

Abstract: A method for implementing a deblocking filter comprising the steps of (A) providing an input buffer storing an unfiltered video frame, (B) providing an output buffer configured to store a filtered video frame, (C) reading pixel values for a plurality of macroblocks from the input buffer into a working buffer, (D) sequentially processing the pixel values in the working buffer through a plurality of filter stages using an array of parallel processors, where each of the plurality of filter stages operates on a different set of pixel values in the working buffer and (E) writing pixel values from a final output region of the working buffer to a respective filter output region of the output buffer.

Abstract: Techniques are disclosed for employing a set of stream processors to greatly accelerate common video encoding and transcoding tasks, with the goal of making these tasks run at a reasonable rate on off-the-shelf hardware. Stream processors are most commonly found in the graphics processing unit (GPU), a commodity piece of computer hardware used to generate images for display. Embodiments of the invention are particularly advantageous to accelerate video encoding and transcoding tasks in which the blocks being processed have dependencies on their neighboring blocks.

Abstract: A method for real time video transmission over networks with varying bandwidth is described. Image quality is maintained even under degrading network performance conditions through the use of image scaling in conjunction with block based motion compensated video coding (MPEG2/4, H.264, et. Al.). The ability to quickly switch resolutions without decreasing reference frame correlation is shown enabling a fast switch to reduce the required bandwidth for stable image quality.

Abstract: Techniques are disclosed for employing a set of stream processors to greatly accelerate common video encoding and transcoding tasks, with the goal of making these tasks run at a reasonable rate on off-the-shelf hardware. Stream processors are most commonly found in the graphics processing unit (GPU), a commodity piece of computer hardware used to generate images for display. Embodiments of the invention are particularly advantageous to accelerate video encoding and transcoding tasks in which the blocks being processed have dependencies on their neighboring blocks.

Abstract: A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.

Abstract: A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.

Abstract: A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.

Abstract: A method for real time video transmission over networks with varying bandwidth is described. Image quality is maintained even under degrading network performance conditions through the use of image scaling in conjunction with block based motion compensated video coding (MPEG2/4, H.264, et. Al.). The ability to quickly switch resolutions without decreasing reference frame correlation is shown enabling a fast switch to reduce the required bandwidth for stable image quality.