Abstract: An embedded processor system having a single-chip embedded microprocessor with analog and digital electrical interfaces to external systems. A novel processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with supervisory control for monitoring and controlling the processor thread state and access to other components. The pipeline enables simultaneous execution of multiple threads by selectively avoiding memory or peripheral access conflicts through the types of pipeline stages chosen and the use of dual and tri-port memory techniques. The single processor core executes one or multiple instruction streams on multiple data streams in various combinations under the control of single or multiple threads.

Abstract: A wireless system for video game control comprised of a base transceiver engaged with an electronic game device where said base transceiver communicates wirelessly with one or more wireless controllers concurrently and which implements a variety of techniques to achieve significant advantages in the areas of latency, reliability, power consumption, and cross platform compatibility.