Abstract: A semiconductor device includes a pad for sense amplifier ground potential as an electrode pad supplying ground potential voltage to a sense amplifier, a first conductive line connected to the pad for sense amplifier ground potential, and a second conductive line connected to an electrode pad closest to the pad for sense amplifier ground potential among plural electrode pads included in a pad row. The second conductive line extends to the opposite side of the first conductive line with the pad row as a reference.
Type:
Grant
Filed:
September 14, 2010
Date of Patent:
December 11, 2012
Assignee:
Elipida Memory, Inc.
Inventors:
Hiromasa Takeda, Satoshi Isa, Shotaro Kobayashi, Mitsuaki Katagiri
Abstract: The invention provides a novel structure of a phase change memory device. In the phase change memory device of the invention, an electrode acting as a radiating fin does not exit immediately above a phase change area of a phase change layer (115). A heater electrode (111) and landing electrode layer (113a, 114a) both contact the bottom of the phase change layer (115) made of GST. The landing electrode layer (113a, 114a) contacts the bottom of the phase change layer (115) to partially overlap in a region off from a portion immediately above the contact face (Y) of the phase change layer and heater electrode. The contact electrode (116, 118) is directly connected to the landing electrode layer (113a, 114a) in a portion off from a portion immediately above the heater electrode (111). The phase change layer of GST or the like does not exist immediately below the contact electrode.
Abstract: A semiconductor memory device comprises: word lines; global bit lines intersecting therewith; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each of which includes memory cells each having a vertical transistor structure connected to the local bit lines at a lower portion and each being formed at an intersection of the word line and the local bit line, and is arranged corresponding to each section of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line.
Abstract: A semiconductor device includes: an active region insulated by an element-isolation insulating film embedded on a semiconductor substrate; multiple element forming sections that are provided in the active region; a semiconductor element that is formed in each of the element forming sections; and a channel stopper that is provided in the active region to insulate the element forming sections from each other. The channel stopper comprises: a fin that protrudes between grooves provided in the element-isolation insulating film and on both sides of the active region; a dummy-gate insulating film that covers the fin; and a dummy gate electrode that straddles the fin.