Patents Assigned to Elite Semiconductor Memory
  • Patent number: 9373378
    Abstract: The semiconductor device incorporates a selected sub word line driver and a first voltage switching circuit. The selected sub word line driver has an input node connected to a selected main word line, an output node connected to a selected sub word line, a reference node supplied with a common reference voltage, and a power node. The first voltage switching circuit selectively supplies a first power voltage, a second power voltage, or the common reference voltage to the power node of the selected sub word line driver. In an active mode, the first voltage switching circuit supplies the first power voltage to pull the selected sub word line to a logic high level. In a precharge mode, the first voltage switching circuit supplies the common reference voltage and then supplies the second power voltage, thereby pulling the selected sub word line to a logic low level. A voltage level of the second power supply node is lower than a voltage level of the first power voltage and higher than the common reference voltage.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: June 21, 2016
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Yi-Fan Chen
  • Patent number: 9300281
    Abstract: A triangular wave generating circuit incorporates a capacitor, first, second, third, and fourth constant current sources, first and second switching units, a high/low level limiter, a clock generator, and a phase detecting unit. The first and second constant current sources charge the capacitor and the third and fourth constant current sources discharge the capacitor. The phase detecting unit compares an externally supplied clock signal with an internal clock signal and generates first and second phase signals base on a phase difference between the externally supplied clock signal and the internal clock signal. The second switching unit comprises a third switch and a fourth switch. The third switch couples the second constant current source to the capacitor in response to the first phase signal. The fourth switch couples the fourth constant current source to the capacitor in response to the second phase signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: March 29, 2016
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Szu-chun Tsao
  • Patent number: 9300276
    Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: March 29, 2016
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Sheng Tung
  • Patent number: 9298557
    Abstract: A method of booting a system with a non-volatile memory device includes at least the following steps: when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein the status flag indicates whether an erase operation applied to the memory block is successfully completed; selectively performing a leakage calibration process upon the memory block according to the status flag; and booting the system according to a boot code stored in the non-volatile memory device.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 29, 2016
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Chung-Shan Kuo, Chih-Hao Chen
  • Publication number: 20150270004
    Abstract: A method for performing an erase operation in a non-volatile memory incorporates the steps of selecting a block on which to perform an erase operation; erasing the selected block using a plurality of erase pulses; receiving erase data of the selected block; determining an over-erase correction verify voltage level based on the erase data; and over-erase correcting the selected block until each cell within the selected block passes the over-erase correction verify voltage level.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 24, 2015
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Cheng-Hung TSAI
  • Patent number: 9141124
    Abstract: A bandgap reference circuit incorporates first, second, and third current sources, an operational amplifier coupled to the second and the third current sources, a voltage divider, a first resistor, and first, second, and third bipolar transistors. The second bipolar transistor has a base configured to receive a first voltage from the voltage divider. The third bipolar transistor has a base configured to receive a second voltage from the voltage divider. The first resistor is coupled between the third current source and the third bipolar transistor.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: September 22, 2015
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Shu-Han Nien
  • Patent number: 9118320
    Abstract: An input buffer includes a first driving circuit, a second driving circuit, a pull up circuit, and a pull down circuit. The first driving circuit is arranged for driving a first input signal to generate an output signal. The second driving circuit is arranged for driving the output signal. The pull up circuit is arranged for selectively controlling the second driving circuit to pull up the output signal according to the first input signal and a second input signal. The pull down circuit is arranged for selectively controlling the second driving circuit to pull down the output signal according to the first input signal and the second input signal.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: August 25, 2015
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Min-Chung Chou
  • Publication number: 20150200659
    Abstract: A triangular wave generating circuit incorporates a capacitor, first, second, third, and fourth constant current sources, first and second switching units, a high/low level limiter, a clock generator, and a phase detecting unit. The first and second constant current sources charge the capacitor and the third and fourth constant current sources discharge the capacitor. The phase detecting unit compares an externally supplied clock signal with an internal clock signal and generates first and second phase signals base on a phase difference between the externally supplied clock signal and the internal clock signal. The second switching unit comprises a third switch and a fourth switch. The third switch couples the second constant current source to the capacitor in response to the first phase signal. The fourth switch couples the fourth constant current source to the capacitor in response to the second phase signal.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Szu-chun TSAO
  • Publication number: 20150155873
    Abstract: An input buffer includes a first driving circuit, a second driving circuit, a pull up circuit, and a pull down circuit. The first driving circuit is arranged for driving a first input signal to generate an output signal. The second driving circuit is arranged for driving the output signal. The pull up circuit is arranged for selectively controlling the second driving circuit to pull up the output signal according to the first input signal and a second input signal. The pull down circuit is arranged for selectively controlling the second driving circuit to pull down the output signal according to the first input signal and the second input signal.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 4, 2015
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Min-Chung Chou
  • Patent number: 9047977
    Abstract: A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode comprises a first frequency dividing unit, a first selection circuit, a second frequency dividing unit, and a second selection circuit. The first frequency dividing unit receives an auto-refresh signal from outside the memory device and generates a plurality of first divided signals. The first selection circuit generates a selection signal selected from the auto-refresh signal and the first divided signals. The second frequency dividing unit divides the frequency of the selection signal and generates a plurality of second divided signals. The second selection circuit generates the refresh execution signal from the selection signal and the second divided signals.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 2, 2015
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Chung Zen Chen
  • Patent number: 9013925
    Abstract: A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells. The staircase voltage generator generates a staircase voltage having a staircase waveform that varies in at least two steps. The decode and level shift circuit selects one of said plurality of bit lines and applies the staircase voltage as a program voltage to the selected bit line.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 21, 2015
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Cheng-Hung Tsai
  • Patent number: 8995100
    Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 31, 2015
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen
  • Patent number: 8995187
    Abstract: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse signals; and programming the memory cells of the M number of groups in response to the respective M number of successive overlapping pulse signals.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: March 31, 2015
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Cheng-Hung Tsai
  • Publication number: 20150058613
    Abstract: A method of booting a system with a non-volatile memory device includes at least the following steps: when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein the status flag indicates whether an erase operation applied to the memory block is successfully completed; selectively performing a leakage calibration process upon the memory block according to the status flag; and booting the system according to a boot code stored in the non-volatile memory device.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventors: Chung-Shan Kuo, Chih-Hao Chen
  • Publication number: 20150023109
    Abstract: A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells. The staircase voltage generator generates a staircase voltage having a staircase waveform that varies in at least two steps. The decode and level shift circuit selects one of said plurality of bit lines and applies the staircase voltage as a program voltage to the selected bit line.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Cheng-Hung Tsai
  • Patent number: 8913442
    Abstract: A circuit for sensing a multi-level cell (MLC) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch. Each of the first decoding units provides a timing information and includes a controlled transistor to allow a current to pass therethrough, and a capacitor to be charged by the current or to discharge through the controlled transistor. The second decoding unit provides a latch signal and includes a controlled transistor to allow a current to pass therethrough, the magnitude of the current being associated with data in an MLC, and a capacitor to be charged by the current or to discharge through the controlled transistor. The data latch, in response to the timing information from each of the first decoding units and the latch signal from the second decoding unit, determines the data in the MLC.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 16, 2014
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Chung Zen Chen, Yi Shin Huang
  • Publication number: 20140301149
    Abstract: A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 9, 2014
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Jen-Shou HSU
  • Patent number: 8848476
    Abstract: A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second booster group receives the supply voltage and generates the first output voltage or a second output voltage according to the detecting signal. The second booster group is composed of a plurality of booster sets connected in parallel, wherein each booster set comprises a plurality of charge pump stages and a plurality of switch units. The number of serially-connected charge pump stages of each booster set in the second booster group is controlled by the plurality of switch units according to the stable voltage levels of the first and second output voltages.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: September 30, 2014
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Chung Shan Kuo
  • Patent number: 8817564
    Abstract: A circuit for sensing a multi-level cell (MLC) comprises a first switch associated with a first read bit, a second switch associated with a second read bit, a first switch control unit to control the first switch in response to a first data bit from a counter, and a second switch control unit to control the second switch in response to a second data bit from the counter.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 26, 2014
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Cheng-Hung Tsai
  • Publication number: 20140219029
    Abstract: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse signals; and programming the memory cells of the M number of groups in response to the respective M number of successive overlapping pulse signals.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 7, 2014
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventor: Cheng-Hung TSAI