Abstract: A method of forming a NAND Flash memory device includes forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the FLASH memory device, the word lines being spaced from each other a distance less than a minimum feature size which can be imaged by a selected photolithography process used in forming at least a portion of the mask layer pattern, and etching the control gate polysilicon layer through the mask layer.

Abstract: A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform the method, an apparatus of automatically determining a sensing timing in a page buffer of a NAND flash memory device is also disclosed. The apparatus includes a first reference bit line, a first current sink, a first reference page buffer, the second reference bit line, a second current sink and a second reference page buffer. The first reference bit line is coupled to the first current sink and the first reference page buffer at both ends thereof. The second reference bit line is coupled to the second current sink and the second reference page buffer at both ends thereof.

Abstract: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

Abstract: A pulse generator comprises a CMOS inverter, a capacitive device and a resistive device, where the CMOS inverter has two terminals connected to a source voltage and a reference voltage, e.g., ground, respectively, the capacitor device and the resistive device are connected to the input end of CMOS inverter, and pulses are generated at the output end of the CMOS inverter. The capacitive device is charged by a boost signal and discharged through the resistive device, so as to manipulate a potential at the input end of the CMOS inverter to control the operations of the transistors included in the CMOS inverter, thereby changing the level of the output voltage of the CMOS inverter. The widths of the pulses can be adjustable by a control signal received by the resistive device.

Abstract: A nonvolatile memory comprises a plurality of memory cells, a bit line control circuit and a verifying circuit. The bit line control circuit includes a driving circuit and a non-driving circuit. The verifying circuit verifies a first threshold voltage of the memory cell when the driving circuit drives the memory cell. The verifying circuit also verifies a second threshold voltage when the driving circuit does not drive the memory cell.

Abstract: A memory device and a method for burn in test are characterized by a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

Abstract: A memory device and a method for burn-in test. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

Abstract: A device comprising a temperature-dependent self refresh circuit for a memory device is provided where the self refresh circuit includes: a temperature sensor circuit for providing an output that reflects an operation temperature; means for switching the temperature sensor circuit to a low power state during a self refresh operation; an encoder for encoding temperature data from said output; and a programmable oscillator responsive to the encoded data to provide a temperature-dependent refresh signal for the self refresh operation.

Abstract: The present self-calibratable oscillating device includes a phase comparator, a clock pad electrically connected to a first input port of the phase comparator, a crystal oscillator electrically connected to a second input port of the phase comparator, an analog/digital converter electrically connected to an output port of the phase comparator, and a memory electrically connected to an output port of the analog/digital converter. The crystal oscillator can be a temperature-compensated crystal oscillator or a surface acoustic wave crystal oscillator. The present self-calibratable oscillating device can further includes a first switch positioned between the first input port of the phase comparator and the clock pad, a second switch positioned between the crystal oscillator and the clock pad wherein the stream direction of the first switch is in reverse of that of the second switch, and a logic control device for controlling the first switch and the second switch.

Abstract: A method of overerase correction for memory cells in a memory array after the memory cells have been erased is provided comprising the following steps: (a) setting a gate voltage of memory cells from a first selected bit line exhibiting leakage current above a threshold value to an initial voltage level; (b) applying a series of overerase correction pulses to the first selected bit line during a selected time period; (c) detecting during the selected time period whether the bit line exhibits leakage current above the threshold value; (d) if the bit line exhibits leakage current above the threshold value after the selected time period, increasing the gate voltage and repeating steps (b) and (c); and (e) if it is detected that the bit line does not exhibit leakage current above the threshold value during the selected time period, selecting a second bit line and repeating steps (a) through (d).

Abstract: A method is provided of regulating a supply voltage for providing a bit line voltage in a semiconductor memory device where the bit line voltage is provided to memory cells in a bit line from the supply voltage through a bit switch. A bit line current provided to the memory cells is detected. The supply voltage is adjusted responsive to the deducted bit line current to at least partially compensate for a voltage drop across the bit switch where the voltage drop is dependent at least in part on the bit line current.

Abstract: A data refresh method of a pseudo static random access memory is implemented by the following procedure. First, an address string and a refresh signal are provided, in which the address string is used for the reference of data reading and writing positions. Secondly, within at least one address of the address string, the active time of a word line of the PSRAM is set to be equivalent to or less than a half of the period of the refresh signal. Then, refreshing performs while the word line is off, and reading and writing are performed while the word line is active. If writing is requested while the word line is off, the writing will be performed when an address transition detection signal ATD switches to the high level in the next address.

Abstract: A timing control method for operating a synchronous memory. The synchronous memory has a local data bus, a signal amplification bus and a global data bus. The timing control method includes manipulating the local data bus, the signal amplification bus and the global bus such that a series of operations including pre-charging the local data buses, developing signals on the amplifier buses is performed evenly within one clock cycle. Amplifying and transferring local data to global data is moved to next cycle and hid within the local data pre-charging period.

Abstract: A memory comprising a memory array, a plurality of word lines, a plurality of bit lines, a word line decoder, an equalizer and an equalization control apparatus is provided to meet the requirement of the completion of bit line equalization prior to the turn on of word lines. The memory array is arranged in columns and rows. The word lines are connected to the rows of the memory array. The bit lines connected to the columns of the memory array. The word line decoder is connected to the word lines for selecting one of the word lines. The equalizer is connected to the bit lines for equalizing the bit lines to a desired voltage. The equalization control apparatus serves for monitoring the equalizer to disable the word line decoder when the equalizer performs a equalization operation and enable the word line decoder when the equalization operation is completed.

Abstract: A regulator for supplying the power of internal circuits, which makes the power of internal circuits independent of the voltage of the outlet power supply by using multi-stage method to control the power supplied from the outlet power source, and avoids the dropping of voltage to affect the system operation. The voltage is able to return to the normal voltage level quickly by increasing the voltage level of the internal circuits in advance, and make the voltage of the internal power supply reduce the variation when output and return to normal voltage level quickly when charge by dynamic adjusting the loading in the regulator.

Abstract: A dynamic random access memory (DRAM) circuit and its associated sub-word-line driver. The DRAM circuit includes a boost circuit, a main word line driver and a sub-word line driver. The boost circuit changes its output boost voltage, which lies between an internal supply voltage and an operating voltage, according to an input row access strobe (RAS) signal. The main word line driver is connected to the output terminal of the boost circuit and the main word line, selected according to input address decoding, is driven by the boost voltage. The sub-word line driver is connected to the main word line. An even or odd sub-word-line signal is generated according to the least significant bit of an input address so that voltage level on the main word line can be used to drive the corresponding sub-word line.

Abstract: A boost circuit for driving word lines in a memory device, comprises: a delaying module for delaying signal to turn on a refresh cycle of the boost circuit; a precharge timing controlling module for controlling the timing of the refresh cycle, wherein the delay module transmitting the signal to the precharge timing controlling module for disabling and enabling the precharge timing controlling module; a precharge module for supplying charge to a first capacitor and a second capacitor, wherein the precharge module is controlled by the precharge timing controlling module; a first capacitor connected to the precharge module and charge the word lines for storing charges; when the precharge module stops to charge the first capacitor, the first capacitor starts to charge the word lines in 2k refresh mode and charge both of the word lines and the second capacitor in 4k refresh mode of the memory device; a second capacitor connected to the precharge module and charge the word lines for storing charges, wherein the sec

Abstract: A laser signature circuit in a memory device comprises input pins for input signal into the memory device; internal circuits of the memory device connected to the input pins; a laser signature circuit connected between the internal circuits, wherein the laser signature circuit comprises a fuse to identify the memory device, the fuse is tested by input a signal into a first input pin of the input pins and the signal is measured on a second input pin of the input pins which is not necessary adjacent to the first input pin.

Abstract: A circuit with variable voltage boosting ratios in a memory device for raising a booster line includes the first and second capacitors, and first and second switching means. The first capacitor electrically connects to the booster line for raising the voltage level on the booster line. The second capacitor couples to the booster line through the first switching means and the power line through the second switching means, respectively. When the first switching means is turned on and the second switching means is turned off, the second capacitor boosts the booster line together with the first capacitor. When the first switching means is turned off and the second switching means is turned on, the second switching means is precharged by the power line instead of boosting the booster line.