Patents Assigned to Elite Semicondutor Memory Technology, Inc.
  • Method of reducing settling time in flash memories and improved flash memory
    Patent number: 7366040
    Abstract: A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing the selected word line with a selected word line voltage for performing the reading operation.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: April 29, 2008
    Assignee: Elite Semicondutor Memory Technology, Inc.
    Inventor: Chung-Zen Chen