Patents Assigned to Elitetech Technology Co., Ltd.
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Patent number: 9129237Abstract: Disclosed is an integrated interfacing system for intelligent defect yield solutions. The integrated interfacing system is configured to have a web server, which initiates a web interface for containing a plurality of functional items provided for clicking to activate a corresponding function. Through the graphical user interface, users may select one or more functions for viewing the multiple solutions regarding wafer yield. The system uses a memory to store the computer-executable instructions for selectively performing corresponding functionalities. When the wafer images are inputted through the interface, the system performs a defect coordinate conversion, dashboard summary, defect screening, defect sampling, defect yield diagnosis, design for yield, yield prediction, pattern diagnosis, data management, and system administration. By the interfacing system, an additional viewing method is also introduced to provision of full-chip viewing over the data retrieved during the wafer manufacturing procedure.Type: GrantFiled: December 28, 2011Date of Patent: September 8, 2015Assignee: ELITETECH TECHNOLOGY CO., LTD.Inventor: Iyun Leu
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Patent number: 8908957Abstract: A method for building a rule of thumb of defect classification is illustrated. Multiple defect classification images with killer defects of examples and all material information of processes associated with the defect, the pattern, and the background are input into the fab tool. The fab tool obtains image characteristics, process characteristics, and image relativity characteristics of the defects, the pattern, and the background in each of the input images, wherein the input images comprises the defect classification images with killer defects of examples. The rule of thumb of the defect classification is built based on the process characteristics, the image characteristics, and the image relativity characteristics of the defects, the pattern, and the background in each of the input images.Type: GrantFiled: December 28, 2011Date of Patent: December 9, 2014Assignee: Elitetech Technology Co.,Ltd.Inventor: Iyun Leu
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Publication number: 20140343884Abstract: Disclosure herein is related to a method and a system for intelligent weak pattern diagnosis for semiconductor product, and a related non-transitory computer-readable storage medium. In the method, a weak pattern layout is firstly retrieved from a defect pattern library and a frequent failure defect pattern library; defect data is retrieved from fab defect inspection tool; a design layout is then received and weak defect pattern screen is performed to extract known and unknown weak defect patterns. In addition to updating the weak pattern library, the weak pattern contour can be made upon SEM image data, and then the true systematic weak pattern can be justified.Type: ApplicationFiled: May 20, 2014Publication date: November 20, 2014Applicant: ELITETECH TECHNOLOGY CO.,LTD.Inventor: IYUN LEU
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Patent number: 8607169Abstract: An intelligent defect diagnosis method for manufacturing fab is provided. The intelligent defect diagnosis method comprises: receiving pluralities of defect data, design layouts and fabrication data; analyzing the defect data, design layouts, and the fabrication data by a defect analysis system, wherein the analyzing step further contains the sub-steps: segmenting and grouping the design layouts into pluralities of multi-pattern group cells to construct LPG cell based pattern groups; introducing the defect data; segmenting defect image into pluralities of defect and pattern contours; mapping the defect data to each multi-pattern group cell to form the LPG based defect composite pattern group; performing coordinate conversion and pattern match between image contour and design layout for coordinate correction; fulfilling CAA with defect contour, pattern contour and design layout, and obtaining corresponding defect yield; classifying the defect type of defect data through defect image classification analysis.Type: GrantFiled: December 28, 2011Date of Patent: December 10, 2013Assignee: Elitetech Technology Co., Ltd.Inventor: Iyun Leu
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Publication number: 20130173041Abstract: Disclosed is an integrated interfacing system for intelligent defect yield solutions. The integrated interfacing system is configured to have a web server, which initiates a web interface for containing a plurality of functional items provided for clicking to activate a corresponding function. Through the graphical user interface, users may select one or more functions for viewing the multiple solutions regarding wafer yield. The system uses a memory to store the computer-executable instructions for selectively performing corresponding functionalities. When the wafer images are inputted through the interface, the system performs a defect coordinate conversion, dashboard summary, defect screening, defect sampling, defect yield diagnosis, design for yield, yield prediction, pattern diagnosis, data management, and system administration. By the interfacing system, an additional viewing method is also introduced to provision of full-chip viewing over the data retrieved during the wafer manufacturing procedure.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: ELITETECH TECHNOLOGY CO.,LTD.Inventor: IYUN LEU
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Publication number: 20130174102Abstract: An intelligent defect diagnosis method for manufacturing fab is provided. The intelligent defect diagnosis method comprises: receiving pluralities of defect data, design layouts and fabrication data; analyzing the defect data, design layouts, and the fabrication data by a defect analysis system, wherein the analyzing step further contains the sub-steps: segmenting and grouping the design layouts into pluralities of multi-pattern group cells to construct LPG cell based pattern groups; introducing the defect data; segmenting defect image into pluralities of defect and pattern contours; mapping the defect data to each multi-pattern group cell to form the LPG based defect composite pattern group; performing coordinate conversion and pattern match between image contour and design layout for coordinate correction; fulfilling CAA with defect contour, pattern contour and design layout, and obtaining corresponding defect yield; classifying the defect type of defect data through defect image classification analysis.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: ELITETECH TECHNOLOGY CO.,LTD.Inventor: IYUN LEU
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Publication number: 20130170733Abstract: A method for building a rule of thumb of defect classification is illustrated. Multiple defect classification images with killer defects of examples and all material information of processes associated with the defect, the pattern, and the background are input into the fab tool. The fab tool obtains image characteristics, process characteristics, and image relativity characteristics of the defects, the pattern, and the background in each of the input images, wherein the input images comprises the defect classification images with killer defects of examples. The rule of thumb of the defect classification is built based on the process characteristics, the image characteristics, and the image relativity characteristics of the defects, the pattern, and the background in each of the input images.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: ELITETECH TECHNOLOGY CO.,LTD.Inventor: IYUN LEU
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Patent number: 8312401Abstract: A method for smart defect review is disclosed. The method includes pre-processing a design layout into a plurality of layout based pattern groups, dividing the design layout into a plurality of cells, overlapping the cells belong to the same layout based pattern groups, extracting a plurality of defect data of all defects on a wafer, constructing a plurality of layout based defect composite pattern groups, executing layout pattern match to obtain each individual layout based defect composite pattern group, performing some defect sample selection rules to each layout based defect composite pattern group, sorting the layout based defect composite pattern groups into different defect types, obtaining a defect image file by reviewing different sample number of defect image from each layout based defect composite pattern group, and generating a defect pattern library or a defect yield prediction by performing a defect yield diagnosis to the defect image file.Type: GrantFiled: January 13, 2011Date of Patent: November 13, 2012Assignee: Elitetech Technology Co., Ltd.Inventors: Iyun Leu, Chin Hsen Lin