Abstract: A memory chiplet includes storage and multiple memory control circuits. Each of the multiple memory control circuits to control a memory access operation to the storage. Multiple channel circuits are employed in the memory chiplet to transfer channel data between the multiple memory control circuits and the storage at a channel bandwidth. Multiple link input/output (I/O) circuits couple the memory chiplet to a host integrated circuit (IC) chiplet. Each of the multiple link I/O circuits transfer link data at a link bandwidth that is free to be different than the channel bandwidth. Bandwidth balancing circuitry, based on relative values between the channel bandwidth and the link bandwidth, selectively configures the multiple channels to transfer a total amount of data at a fully-available link bandwidth of the multiple links or selectively configure the multiple links to transfer the total amount of data at a fully-available channel bandwidth of the multiple channels.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

Abstract: A multi-chip module (MCM) includes a first integrated circuit (IC) chip including a first interface defining a first number of interface contacts. Conversion circuitry receives a first set of information-carrying signals associated with a memory access operation. Conversion circuitry generates a second set of non-information-carrying signals associated with the memory access operation and aggregates the second set of non-information-carrying signals with the first set of information-carrying signals to generate an aggregate set of signals. A second interface transmits the aggregate set of signals. Memory, including a memory interface coupled to the second interface of the first IC chiplet, receives the aggregate set of signals.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes an active silicon substrate and a memory interface circuit configured to support N memory channels. The memory interface circuit has a primary interface for coupling to a host memory interface via the N memory channels. A first HBM stack of memory die is disposed on the active silicon substrate and coupled to a secondary interface of the memory interface circuit. The first HBM stack dedicated to a first subset of the N data channels and a first data transfer rate. A second HBM stack of memory die is disposed on the active silicon substrate. The second HBM stack is positioned inline with the first HBM stack and the memory interface circuit and coupled to the secondary interface of the memory interface circuit. The second HBM stack is dedicated to a second subset of the N data channels and exhibits a second data transfer rate.

Abstract: An integrated circuit (IC) chiplet includes a die-to-die (D2D) interface with a cyclic redundancy check (CRC) decoder to process a received data block of N bits that is appended with a transmit-side CRC-16 checksum. The CRC decoder includes checksum circuitry and storage to store N unique non-zero checksum error values. Each of the N unique non-zero checksum error values represents a predicted checksum error value in the event a given bit location in the received data block of N bits is in error. Match circuitry indicates a match of a generated non-zero error checksum value to one of the N unique non-zero checksum error values in the storage. Repair circuitry corrects the given bit location corresponding to the match.

Abstract: Systems and methods are provided for a system in a package (SiP) connectivity using one or more ultra short reach (USR) chiplets. The USR chiplet can receive/transmit data at a lower throughput and transmit/receive that data at a higher throughput over ultra short distances. The USR chiplet can be connected to a main integrated circuit (IC) using a high density interconnect or integrated with the main IC in a mold material. The USR chip can enable the main IC to transfer data over a substrate at a higher speed using a fewer number of traces.

Abstract: A physical layer interconnect between chips/chiplets provides high bandwidth communication with low power requirements using an organic substrate such as a printed circuit board. An interface between first and second chiplets uses a separate chiplet, or a combination logic die and interconnect interface, interfacing with the interconnect. A connection between a computing device and a memory can be longer, allowing the computing device to be coupled to more memories, expansion slots, or external connections. The interconnect can route memory commands between computing devices and memories, allowing multiple and different computing devices to be coupled to each other or to multiple and different memories. The memories can perform in-memory computing using chiplets coupled thereto. The interconnect couples to possibly different computing devices and possibly different memories, such as in a rack configuration, including CPUs or GPUs. The specialized processing devices can include one or more TPUs or VPUs.