Abstract: A phase locked loop circuit employing a single phase detector provides limited maximum lock time by avoiding hang-up. The circuit first establishes a gross indication of phase relation sufficient to establish a direction of phase shift away from the unstable equilibrium point. The phase is then shifted by a predetermined value to establish a bounded phase relation exclusive of the unstable equilibrium point and inclusive of the stable equilibrium point. Conventional phase locking then provides the desired frequency and phase relation, but without potential for hang-up.
Type:
Grant
Filed:
August 6, 1990
Date of Patent:
November 16, 1999
Assignees:
Elko Corp., Seiko Epson Corp
Inventors:
Bruce C. Nepple, Jeffrey R. Owen, Daniel J. Park