Abstract: The present invention provides for operation of a digital communication receiver having multiple operational modes so that power consumption of the system can be kept at a minimum by using the lowest power operation for the system components performing tasks associated with each of the respective one of the multiple operational modes. An example is the receiver A/D converter operation with the lowest power to provide the desired resolution. Also, the invention provides novel architectures for implementing scalable resolution A/D converters. Furthermore, the invention generally includes a novel architecture for controlling the dynamic range of an A/D converter. In addition, the invention generally involves novel architectures for controlling the dynamic range of an A/D converter to alleviate difficulties associated with AGC control loops. Multiple exemplary embodiments are disclosed.

Abstract: According to one aspect of the invention, a system is provided which includes an adaptive compensation component and a conversion component. The adaptive compensation component performs spectral and linearity compensation on input digital signals to generate output digital signals that are compensated against spectral and linearity variations in the system. The conversion component is coupled to the adaptive compensation component and performs conversion between digital and analog formats. The conversion component receives digital signals generated by the adaptive compensation component and converts the received digital signals to analog format. The conversion component also receives analog signals and converts the received analog signals to digital format for inputted to the adaptive compensation component.

Abstract: This invention relates to matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors. The method also includes examining fields of the interconnected design factors and mapping the interconnected design vectors into specific hardware and software elements.

Abstract: According to one aspect of the invention, a system is provided which includes a transmitting node and one or more communication channels. The transmitting node includes one or more components to process data for transmission to a receiving node over the one or more communication channels. In one embodiment of the invention, the power consumption levels of one or more components in the transmitting node are determined based on data transmission rates supported by the transmitting node and data transmission rates supported by the one or more channels.

Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes decomposing the matched instruction set processor system into interconnected design vectors, each of the interconnected design vectors including a binding header method, a run method, a conjugate virtual machine (CVM), a binding trailer method, and an invocation method. The method also includes analyzing and mapping the interconnected design vectors into a re-configurable platform.

Abstract: According to one embodiment of the present invention, a method and system for VLSI hardware design and synthesis is provided in which components provided by a heterogeneous modeling framework are interconnected, based on design specifications of a VLSI, to create a corresponding behavioral VLSI model. The heterogeneous modeling framework contains a first component library including logic functions that can be used to build hardware structural models and a second component library including numeric standard. The created model is simulated, tested, and functionally verified using discrete event domain simulation capabilities provided by the heterogeneous framework. A corresponding structural model is extracted from the tested behavioral VLSI model using a software tool provided by the heterogeneous modeling framework.

Abstract: According to one aspect of the invention, an apparatus is provided which includes one or more analog components, an analog to digital (A/D) converter, and a spectral compensator. The operational characteristics of the one or more analog components have variations based on input signal frequency. The one or more analog components perform their corresponding operations with respect to an input analog signal to generate an output analog signal. The analog to digital (A/D) converter is coupled to receive the output analog signal from the one or more analog components and to convert the output analog signal to a digital signal. The spectral compensator is coupled to receive the digital signal generated by the A/D converter and to compensate spectral characteristics of the digital signal based on variations in the operational characteristics of the one or more analog components.