Abstract: A method and apparatus are disclosed for prefragmenting or presegmenting data. A data protocol type and length are provided. Based on the type and length, a linked list memory buffer structure is determined. Locations within the memory buffer structure for storage of data therein is also determined allowing for sufficient unused memory therein to support one of a fragmentation operation and a segmentation operation subsequent to memory allocation. As such, further memory allocation during a fragmentation operation or a segmentation operation is obviated. The determined memory buffer structure is then allocated.

Abstract: A method for reducing the memory requirements of executing ciphering processes is disclosed which utilizes sequential key extraction and ciphering. By providing a base key for extracting therefrom multiple first sequential security keys; each key is sequentially extracted and employed. During the process overwriting of each sequential security key occurs with the next subsequently extracted sequential security key. In this manner memory requirements are lowered, power consumption reduced which are important in mobile applications.

Abstract: A method of implementing large number multiplication and exponentiation is provided upon a general purpose microprocessor. These large number multiplication and exponentiation processes being common to cryptography standards such as RSA and AES that typically employ numbers with 512-bits, 1024-bits, and 2048-bits. According to the invention the method establishes the size of the large number processes according to value stored within a control register, this control register and other registers storing data are configured according to this value and accessed as N-bit registers (i.e. as 1024-bit registers for 1024-bit encryption. Additionally, the multiplication and exponentiation processes are handled according to the size of an arithmetic primitive, which is established according to the hardware configuration upon which the process is operating.

Abstract: The invention relates to the field of data packet management, and more specifically to the field of managing of data packets in such a manner that power consumption is reduced, such reduction being especially beneficial for portable device applications. In accordance with an embodiment of the invention there is provided a method of handling and manipulating data wherein padding and unpadding operations for a packet of data are performed at the transmission/reception of a packet from a network, and data handling is minimized within the portable device. According to another embodiment of the invention there is provided a method of encryption for packet data absent the padding data.

Abstract: A method of multiplying large integers is disclosed. Two large numbers, x and y, are provided. values are determined in accordance with the Karatsuba multiplication process based on x and y. A first and second value according to the Karatsuba multiplication method are also determined. The third value for use in accordance with the Karatsuba multiplication method is determined by determining C?=(x1+x2)[m?1:0]*(y1+y2)[m?1:0] and determining C=C?+((y1+y2)[2m:2m] AND (x1+x2)[m?1:0]+(x1+x2)[2m:2m] AND (y1+y2)[m:0])<<m, where << is a bitwise shift operation, wherein AND is performed by performing a Boolean AND of a single bit within a first operand with each bit within a second operand and wherein D[j:k] refers to the jth to kth bits of D.

Abstract: First and second functional circuit blocks (FCBs) control the operation of a clock circuits coupled thereto in dependence upon processing requirements of the FCBs as well as power consumption considerations. When the FCB is not processing data, the clock circuit coupled to that FCB has one of its clock signal frequency reduced or is disabled so that the FCB consumes significantly reduced amounts of electrical power. Through controlling clock frequency and enabling and disabling of the clock circuit, electrical power consumption of the FCB is advantageously reduced.

Abstract: A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is retrieved and stored in a corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. The DMA process is performed absent retrieving the same data a second other time prior to storing of same within the corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations.

Abstract: An architecture for use in packet processing and supporting compatibility with current BSD implementations for packet processing is proposed wherein two MBUF formats are supported. A first format includes a header portion and a data portion for storing data therein. A second format includes a header portion but is absent a data portion and is for addressing data stored within a cluster and external to the MBUF itself.