Abstract: Alternating current from a source is supplied to a load through a thyristor whose gate electrode is controlled by the output from a zero voltage switch. The zero voltage switch is enabled by the output of a flip-flop beginning at the simultaneous occurrence of a command input and a clock signal input to the flip-flop. The clock signal input is generated just before the beginning of each half cycle of a predetermined polarity of the alternating current so that integral cycling is achieved without delayed switching which would produce current spikes.