Abstract: A network switching hub is implemented on an IC chip, and has a bus connected to external ports through sets of queue switch transistors, source to drain for data switched onto the bus, the queue switch transistors gated simultaneously by control lines from an on-board arbitrator controller following a preprogrammed arbitration scheme. Data is switched off the bus and hub by port adapter controllers connected to read amplifier receivers connected directly to the on-chip bus, the port adapter controllers enabled by the arbitrator controller following the same preprogrammed arbitration scheme. Ports may be serial or parallel, and may be adapted to special purposes, such as PCI and hub to hub connection for expansion.